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rtio: expose full_ts_width instead of counter_width parameter

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This commit is contained in:
Sebastien Bourdeauducq 2015-04-28 01:38:11 +08:00
parent dc14728264
commit 27d94a22de
1 changed files with 3 additions and 3 deletions
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6
artiq/gateware/rtio/core.py
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@ -281,7 +281,7 @@ class _KernelCSRs(AutoCSR):
class RTIO(Module):
def __init__(self, channels, clk_freq, counter_width=63,
def __init__(self, channels, clk_freq, full_ts_width=63,
guard_io_cycles=20):
data_width = max(rtlink.get_data_width(c.interface)
for c in channels)
@ -293,7 +293,7 @@ class RTIO(Module):
# CSRs
self.kcsrs = _KernelCSRs(bits_for(len(channels)-1),
data_width, address_width,
counter_width + fine_ts_width)
full_ts_width)
# Clocking/Reset
# Create rsys and rio domains based on sys and rio
@ -309,7 +309,7 @@ class RTIO(Module):
self.kcsrs.reset.storage)
# Managers
self.submodules.counter = _RTIOCounter(counter_width)
self.submodules.counter = _RTIOCounter(full_ts_width - fine_ts_width)
i_datas, i_timestamps = [], []
o_statuses, i_statuses = [], []