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urukul: fix typos

This commit is contained in:
Sebastien Bourdeauducq 2019-01-21 19:37:33 +08:00
parent 9bbb67c340
commit 222825d3a8
2 changed files with 2 additions and 2 deletions
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2
artiq/coredevice/ad9910.py
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@ -427,7 +427,7 @@ class AD9910:
This method first locates a valid SYNC_IN delay at zero validation This method first locates a valid SYNC_IN delay at zero validation
window size (setup/hold margin) by scanning around `search_seed`. It window size (setup/hold margin) by scanning around `search_seed`. It
then looks for similar valid delays at successively larger validation then looks for similar valid delays at successively larger validation
window sizes until none can be found. It then deacreses the validation window sizes until none can be found. It then decreases the validation
window a bit to provide some slack and stability and returns the window a bit to provide some slack and stability and returns the
optimal values. optimal values.

2
artiq/coredevice/urukul.py
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@ -327,7 +327,7 @@ class CPLD:
and align it to the current RTIO timestamp. and align it to the current RTIO timestamp.
The SYNC_IN signal is derived from the coarse RTIO clock The SYNC_IN signal is derived from the coarse RTIO clock
and the divider must be a power of two two. and the divider must be a power of two.
Configure ``sync_sel == 0``. Configure ``sync_sel == 0``.
:param div: SYNC_IN frequency divider. Must be a power of two. :param div: SYNC_IN frequency divider. Must be a power of two.