occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

sayma_amc: expose RTM fpga load pins as GPIOs

This commit is contained in:
Robert Jördens 2018-02-28 16:45:55 +00:00 committed by Robert Jordens
parent cedecc3030
commit 1f999c7f5f
1 changed files with 11 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
artiq/gateware/targets/sayma_amc.py
View File

@ -161,9 +161,17 @@ class Standalone(MiniSoC, AMPSoC):
] ]
# RTM bitstream upload # RTM bitstream upload
rtm_fpga_cfg = platform.request("rtm_fpga_cfg") slave_fpga_cfg = self.platform.request("rtm_fpga_cfg")
self.submodules.rtm_fpga_cfg = SlaveFPGA(rtm_fpga_cfg) self.submodules.slave_fpga_cfg = gpio.GPIOTristate([
self.csr_devices.append("rtm_fpga_cfg") slave_fpga_cfg.cclk,
slave_fpga_cfg.din,
slave_fpga_cfg.done,
slave_fpga_cfg.init_b,
slave_fpga_cfg.program_b,
])
self.csr_devices.append("slave_fpga_cfg")
self.config["HAS_SLAVE_FPGA"] = None
self.config["SLAVE_FPGA_GATEWARE"] = 0xde0000
# AMC/RTM serwb # AMC/RTM serwb
serwb_pll = serwb.phy.SERWBPLL(125e6, 625e6, vco_div=2) serwb_pll = serwb.phy.SERWBPLL(125e6, 625e6, vco_div=2)