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firmware: Fix Si5324 initialisation for satellites 

Commit 740543d4e2 had unintentionally broken DRTIO
satellites, as si5324::setup is also used there. This
imports setup_si5324_as_synthesizer() from artiq-zynq,
where the input selection was already explicitly done.

GitHub: Fixes #2028.
This commit is contained in:
David Nadlinger 2022-12-17 02:06:22 +00:00
parent ce57d6c346
commit 1db3a42ad7
2 changed files with 96 additions and 77 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/firmware/libboard_artiq/si5324.rs
View File

@ -214,11 +214,9 @@ pub fn bypass(input: Input) -> Result<()> {
Ok(())
}
pub fn setup(settings: &FrequencySettings, ext_input: Input) -> Result<()> {
pub fn setup(settings: &FrequencySettings, input: Input) -> Result<()> {
let s = map_frequency_settings(settings)?;
// FREE_RUN=1 routes XA/XB to CKIN2.
let input = if settings.crystal_ref { Input::Ckin2 } else { ext_input };
let cksel_reg = match input {
Input::Ckin1 => 0b00,
Input::Ckin2 => 0b01,

43
artiq/firmware/runtime/rtio_clocking.rs
View File

@ -130,9 +130,10 @@ const SI5324_EXT_INPUT: si5324::Input = si5324::Input::Ckin2;
#[cfg(si5324_as_synthesizer)]
fn setup_si5324_as_synthesizer(cfg: RtioClock) {
let si5324_settings = match cfg {
let (si5324_settings, si5324_ref_input) = match cfg {
RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
(
si5324::FrequencySettings {
n1_hs : 10,
nc1_ls : 4,
@ -142,10 +143,13 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
n32 : 6,
bwsel : 4,
crystal_ref: false
}
},
SI5324_EXT_INPUT
)
},
RtioClock::Ext0_Synth0_100to125 => { // 125MHz output, from 100MHz CLKINx reference, 586 Hz loop bandwidth
info!("using 100MHz reference to make 125MHz RTIO clock with PLL");
(
si5324::FrequencySettings {
n1_hs : 10,
nc1_ls : 4,
@ -155,10 +159,13 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
n32 : 52,
bwsel : 4,
crystal_ref: false
}
},
SI5324_EXT_INPUT
)
},
RtioClock::Ext0_Synth0_125to125 => { // 125MHz output, from 125MHz CLKINx reference, 606 Hz loop bandwidth
info!("using 125MHz reference to make 125MHz RTIO clock with PLL");
(
si5324::FrequencySettings {
n1_hs : 5,
nc1_ls : 8,
@ -168,10 +175,13 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
n32 : 63,
bwsel : 4,
crystal_ref: false
}
},
SI5324_EXT_INPUT
)
},
RtioClock::Int_150 => { // 150MHz output, from crystal
info!("using internal 150MHz RTIO clock");
(
si5324::FrequencySettings {
n1_hs : 9,
nc1_ls : 4,
@ -181,10 +191,13 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
n32 : 7139,
bwsel : 3,
crystal_ref: true
}
},
RtioClock::Int_100 => { // 100MHz output, from crystal. Also used as reference for Sayma HMC830.
si5324::Input::Ckin2
)
},
RtioClock::Int_100 => { // 100MHz output, from crystal
info!("using internal 100MHz RTIO clock");
(
si5324::FrequencySettings {
n1_hs : 9,
nc1_ls : 6,
@ -194,10 +207,13 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
n32 : 7139,
bwsel : 3,
crystal_ref: true
}
},
si5324::Input::Ckin2
)
},
RtioClock::Int_125 => { // 125MHz output, from crystal, 7 Hz
info!("using internal 125MHz RTIO clock");
(
si5324::FrequencySettings {
n1_hs : 10,
nc1_ls : 4,
@ -207,10 +223,13 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
n32 : 4565,
bwsel : 4,
crystal_ref: true
}
}
},
si5324::Input::Ckin2
)
},
_ => { // 125MHz output like above, default (if chosen option is not supported)
warn!("rtio_clock setting '{:?}' is not supported. Falling back to default internal 125MHz RTIO clock.", cfg);
(
si5324::FrequencySettings {
n1_hs : 10,
nc1_ls : 4,
@ -220,10 +239,12 @@ fn setup_si5324_as_synthesizer(cfg: RtioClock) {
n32 : 4565,
bwsel : 4,
crystal_ref: true
}
},
si5324::Input::Ckin2
)
}
};
si5324::setup(&si5324_settings, SI5324_EXT_INPUT).expect("cannot initialize Si5324");
si5324::setup(&si5324_settings, si5324_ref_input).expect("cannot initialize Si5324");
}
pub fn init() {