Merge branch 'master' of github.com:m-labs/artiq

artiq/compiler/transforms/asttyped_rewriter.py

@@ -477,7 +477,7 @@ class ASTTypedRewriter(algorithm.Transformer):
             target=node.target, iter=node.iter, body=node.body, orelse=node.orelse,
             trip_count=None, trip_interval=None,
             keyword_loc=node.keyword_loc, in_loc=node.in_loc, for_colon_loc=node.for_colon_loc,
-            else_loc=node.else_loc, else_colon_loc=node.else_colon_loc)
+            else_loc=node.else_loc, else_colon_loc=node.else_colon_loc, loc=node.loc)
         return node
 
     def visit_withitem(self, node):

artiq/frontend/artiq_flash.py

@@ -6,7 +6,6 @@ import os
 import subprocess
 import tempfile
 
-import artiq
 from artiq import __artiq_dir__ as artiq_dir
 from artiq.frontend.bit2bin import bit2bin
 
@@ -18,13 +17,13 @@ def get_argparser():
         epilog="""\
 Valid actions:
 
-    * proxy: load the flash proxy bitstream
+    * proxy: load the flash proxy gateware bitstream
-    * bitstream: write bitstream to flash
+    * gateware: write gateware bitstream to flash
     * bios: write bios to flash
     * runtime: write runtime to flash
     * storage: write storage image to flash
-    * load: load bitstream into device (volatile but fast)
+    * load: load gateware bitstream into device (volatile but fast)
-    * start: trigger the target to (re)load its bitstream from flash
+    * start: trigger the target to (re)load its gateware bitstream from flash
 
 Prerequisites:
 
@@ -42,7 +41,7 @@ Prerequisites:
     parser.add_argument("-f", "--storage", help="write file to storage area")
     parser.add_argument("-d", "--dir", help="look for files in this directory")
     parser.add_argument("ACTION", nargs="*",
-                        default="proxy bitstream bios runtime start".split(),
+                        default="proxy gateware bios runtime start".split(),
                         help="actions to perform, default: %(default)s")
     return parser
 
@@ -55,7 +54,7 @@ def main():
         "kc705": {
             "chip": "xc7k325t",
             "start": "xc7_program xc7.tap",
-            "bitstream": 0x000000,
+            "gateware": 0x000000,
             "bios": 0xaf0000,
             "runtime": 0xb00000,
             "storage": 0xb80000,
@@ -63,7 +62,7 @@ def main():
         "pipistrello": {
             "chip": "xc6slx45",
             "start": "xc6s_program xc6s.tap",
-            "bitstream": 0x000000,
+            "gateware": 0x000000,
             "bios": 0x170000,
             "runtime": 0x180000,
             "storage": 0x200000,
@@ -83,23 +82,23 @@ def main():
             proxy_base = "bscan_spi_{}.bit".format(config["chip"])
             proxy = None
             for p in [opts.dir, os.path.expanduser("~/.migen"),
-                    "/usr/local/share/migen", "/usr/share/migen"]:
+                      "/usr/local/share/migen", "/usr/share/migen"]:
                 proxy_ = os.path.join(p, proxy_base)
                 if os.access(proxy_, os.R_OK):
                     proxy = "jtagspi_init 0 {}".format(proxy_)
                     break
             if not proxy:
                 raise SystemExit(
-                    "proxy bitstream {} not found".format(proxy_base))
+                    "proxy gateware bitstream {} not found".format(proxy_base))
             prog.append(proxy)
-        elif action == "bitstream":
+        elif action == "gateware":
             bin = os.path.join(opts.dir, "top.bin")
             if not os.access(bin, os.R_OK):
                 bin = tempfile.mkstemp()[1]
                 bit = os.path.join(opts.dir, "top.bit")
                 conv = True
             prog.append("jtagspi_program {} 0x{:x}".format(
-                bin, config["bitstream"]))
+                bin, config["gateware"]))
         elif action == "bios":
             prog.append("jtagspi_program {} 0x{:x}".format(
                 os.path.join(opts.dir, "bios.bin"), config["bios"]))

doc/manual/installing.rst

@@ -93,11 +93,11 @@ Preparing the core device FPGA board
 
 You now need to flash 3 things on the FPGA board:
 
-1. The FPGA bitstream
+1. The FPGA gateware bitstream
 2. The BIOS
 3. The ARTIQ runtime
 
-They are all shipped in our Conda packages, along with the required flash proxy bitstreams.
+They are all shipped in our Conda packages, along with the required flash proxy gateware bitstreams.
 
 First you need to install OpenOCD. Then, you can flash the board:
 
@@ -169,11 +169,11 @@ and the ARTIQ kernels.
 Preparing the core device FPGA board
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-These steps are required to generate bitstream (``.bit``) files, build the MiSoC BIOS and ARTIQ runtime, and flash FPGA boards. If the board is already flashed, you may skip those steps and go directly to `Installing the host-side software`.
+These steps are required to generate gateware bitstream (``.bit``) files, build the MiSoC BIOS and ARTIQ runtime, and flash FPGA boards. If the board is already flashed, you may skip those steps and go directly to `Installing the host-side software`.
 
 * Install the FPGA vendor tools (e.g. Xilinx ISE and/or Vivado):
 
-    * Get Xilinx tools from http://www.xilinx.com/support/download/index.htm. ISE can build bitstreams both for boards using the Spartan-6 (Pipistrello) and 7-series devices (KC705), while Vivado supports only boards using 7-series devices.
+    * Get Xilinx tools from http://www.xilinx.com/support/download/index.htm. ISE can build gateware bitstreams both for boards using the Spartan-6 (Pipistrello) and 7-series devices (KC705), while Vivado supports only boards using 7-series devices.
 
     * The Pipistrello is supported by Webpack, the KC705 is not.
 
@@ -208,9 +208,9 @@ These steps are required to generate bitstream (``.bit``) files, build the MiSoC
 
 .. _install-flash-proxy:
 
-* Install the required flash proxy bitstreams:
+* Install the required flash proxy gateware bitstreams:
 
-    The purpose of the flash proxy bitstream is to give programming software fast JTAG access to the flash connected to the FPGA.
+    The purpose of the flash proxy gateware bitstream is to give programming software fast JTAG access to the flash connected to the FPGA.
 
     * Pipistrello and KC705:
 
@@ -243,7 +243,7 @@ These steps are required to generate bitstream (``.bit``) files, build the MiSoC
     :ref:`installing the host-side software <installing-the-host-side-software>`.
 
 
-* Build the bitstream, BIOS and runtime by running:
+* Build the gateware bitstream, BIOS and runtime by running:
     ::
 
         $ cd ~/artiq-dev
@@ -270,7 +270,7 @@ These steps are required to generate bitstream (``.bit``) files, build the MiSoC
 
 .. note:: The `-t` option specifies the board your are targeting. Available options are ``kc705`` and ``pipistrello``.
 
-* Check that the board boots by running a serial terminal program (you may need to press its FPGA reconfiguration button or power-cycle it to load the bitstream that was newly written into the flash): ::
+* Check that the board boots by running a serial terminal program (you may need to press its FPGA reconfiguration button or power-cycle it to load the gateware bitstream that was newly written into the flash): ::
 
         $ make -C ~/artiq-dev/misoc/tools # do only once
         $ ~/artiq-dev/misoc/tools/flterm --port /dev/ttyUSB1