occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

gateware/rtio/analyzer: fix event ordering

This commit is contained in:
Sebastien Bourdeauducq 2015-12-19 17:04:30 +08:00
parent afee03b89c
commit 1638f0fa9b
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/rtio/analyzer.py
View File

@ -214,7 +214,7 @@ class Analyzer(Module, AutoCSR):
self.submodules.message_encoder = MessageEncoder(rtio_core)
self.submodules.converter = stream.Converter(
[("data", 256)], [("data", dw)])
[("data", 256)], [("data", dw)], reverse=True)
self.submodules.fifo = stream.SyncFIFO(
[("data", dw)], fifo_depth, True)
self.submodules.dma = DMAWriter(membus)