occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

ad9910/set_mu: comment on caveats when setting register

This commit is contained in:
occheung 2021-12-07 14:30:22 +08:00
parent 41b2c8d07a
commit 1064fdff2e
1 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
artiq/coredevice/ad9910.py
View File

@ -523,7 +523,12 @@ class AD9910:
This uses machine units (FTW, POW, ASF). The frequency tuning word
width is 32, the phase offset word width is 16, and the amplitude
scale factor width is 14.
scale factor width is 14. When profile is set to -1 for RAM mode, ftw,
pow_ and asf parameters may not have an impact depending on the RAM
data destination. For example, the value in the FTW register will not
impact the waveform generated by frequency RAM mode. Refer to the
datasheet regarding the source of amplitude, frequency and phase in any
mode of operations.
After the SPI transfer, the shared IO update pin is pulsed to
activate the data.