drtio: forward destination with channel

artiq/gateware/drtio/rt_controller_master.py

@@ -93,11 +93,10 @@ class RTController(Module):
         ]
 
         # common packet fields
-        chan_sel = self.cri.chan_sel[:16]
         rt_packet_buffer_request = Signal()
         rt_packet_read_request = Signal()
         self.comb += [
-            rt_packet.sr_channel.eq(chan_sel),
+            rt_packet.sr_chan_sel.eq(self.cri.chan_sel),
             rt_packet.sr_address.eq(self.cri.o_address),
             rt_packet.sr_data.eq(self.cri.o_data),
             rt_packet.sr_timestamp.eq(self.cri.timestamp),

artiq/gateware/drtio/rt_packet_master.py

@@ -26,7 +26,7 @@ class RTPacketMaster(Module):
         self.sr_ack = Signal()
         self.sr_notwrite = Signal()
         self.sr_timestamp = Signal(64)
-        self.sr_channel = Signal(16)
+        self.sr_chan_sel = Signal(24)
         self.sr_address = Signal(16)
         self.sr_data = Signal(512)
 
@@ -85,19 +85,19 @@ class RTPacketMaster(Module):
 
         # Write FIFO and extra data count
         sr_fifo = ClockDomainsRenamer({"write": "sys_with_rst", "read": "rtio_with_rst"})(
-            AsyncFIFO(1+64+16+16+512, sr_fifo_depth))
+            AsyncFIFO(1+64+24+16+512, sr_fifo_depth))
         self.submodules += sr_fifo
         sr_notwrite_d = Signal()
         sr_timestamp_d = Signal(64)
-        sr_channel_d = Signal(16)
+        sr_chan_sel_d = Signal(24)
         sr_address_d = Signal(16)
         sr_data_d = Signal(512)
         self.comb += [
             sr_fifo.we.eq(self.sr_stb),
             self.sr_ack.eq(sr_fifo.writable),
-            sr_fifo.din.eq(Cat(self.sr_notwrite, self.sr_timestamp, self.sr_channel,
+            sr_fifo.din.eq(Cat(self.sr_notwrite, self.sr_timestamp, self.sr_chan_sel,
                                self.sr_address, self.sr_data)),
-            Cat(sr_notwrite_d, sr_timestamp_d, sr_channel_d,
+            Cat(sr_notwrite_d, sr_timestamp_d, sr_chan_sel_d,
                 sr_address_d, sr_data_d).eq(sr_fifo.dout)
         ]
 
@@ -114,7 +114,7 @@ class RTPacketMaster(Module):
 
         sr_notwrite = Signal()
         sr_timestamp = Signal(64)
-        sr_channel = Signal(16)
+        sr_chan_sel = Signal(24)
         sr_address = Signal(16)
         sr_extra_data_cnt = Signal(8)
         sr_data = Signal(512)
@@ -122,7 +122,7 @@ class RTPacketMaster(Module):
         self.sync.rtio += If(sr_fifo.re,
             sr_notwrite.eq(sr_notwrite_d),
             sr_timestamp.eq(sr_timestamp_d),
-            sr_channel.eq(sr_channel_d),
+            sr_chan_sel.eq(sr_chan_sel_d),
             sr_address.eq(sr_address_d),
             sr_data.eq(sr_data_d))
 
@@ -230,7 +230,7 @@ class RTPacketMaster(Module):
         tx_fsm.act("WRITE",
             tx_dp.send("write",
                 timestamp=sr_timestamp,
-                channel=sr_channel,
+                chan_sel=sr_chan_sel,
                 address=sr_address,
                 extra_data_cnt=sr_extra_data_cnt,
                 short_data=sr_data[:short_data_len]),
@@ -252,14 +252,14 @@ class RTPacketMaster(Module):
             )
         )
         tx_fsm.act("BUFFER_SPACE",
-            tx_dp.send("buffer_space_request", destination=sr_channel),
+            tx_dp.send("buffer_space_request", destination=sr_chan_sel[16:]),
             If(tx_dp.packet_last,
                 sr_buf_re.eq(1),
                 NextState("IDLE")
             )
         )
         tx_fsm.act("READ",
-            tx_dp.send("read_request", channel=sr_channel, timeout=sr_timestamp),
+            tx_dp.send("read_request", chan_sel=sr_chan_sel, timeout=sr_timestamp),
             If(tx_dp.packet_last,
                 sr_buf_re.eq(1),
                 NextState("IDLE")

artiq/gateware/drtio/rt_packet_repeater.py

@@ -35,12 +35,12 @@ class RTPacketRepeater(Module):
 
         # Write buffer and extra data count
         wb_timestamp = Signal(64)
-        wb_channel = Signal(16)
+        wb_chan_sel = Signal(24)
         wb_address = Signal(16)
         wb_data = Signal(512)
         self.sync.rtio += If(self.cri.cmd == cri.commands["write"],
             wb_timestamp.eq(self.cri.timestamp),
-            wb_channel.eq(self.cri.chan_sel),
+            wb_chan_sel.eq(self.cri.chan_sel),
             wb_address.eq(self.cri.o_address),
             wb_data.eq(self.cri.o_data))
 
@@ -100,7 +100,7 @@ class RTPacketRepeater(Module):
         tx_fsm.act("WRITE",
             tx_dp.send("write",
                 timestamp=wb_timestamp,
-                channel=wb_channel,
+                chan_sel=wb_chan_sel,
                 address=wb_address,
                 extra_data_cnt=wb_extra_data_cnt,
                 short_data=wb_data[:short_data_len]),

artiq/gateware/drtio/rt_packet_satellite.py

@@ -83,12 +83,12 @@ class RTPacketSatellite(Module):
                 rx_dp.packet_as["set_time"].timestamp),
             If(load_read_request | read_request_pending,
                 self.cri.chan_sel.eq(
-                    rx_dp.packet_as["read_request"].channel),
+                    rx_dp.packet_as["read_request"].chan_sel),
                 self.cri.timestamp.eq(
                     rx_dp.packet_as["read_request"].timeout)
             ).Else(
                 self.cri.chan_sel.eq(
-                    rx_dp.packet_as["write"].channel),
+                    rx_dp.packet_as["write"].chan_sel),
                 self.cri.timestamp.eq(
                     rx_dp.packet_as["write"].timestamp)
             ),

artiq/gateware/drtio/rt_serializer.py

@@ -49,13 +49,13 @@ def get_m2s_layouts(alignment):
     plm.add_type("set_time", ("timestamp", 64))
 
     plm.add_type("write", ("timestamp", 64),
-                          ("channel", 16),
+                          ("chan_sel", 24),
                           ("address", 16),
                           ("extra_data_cnt", 8),
                           ("short_data", short_data_len))
     plm.add_type("buffer_space_request", ("destination", 8))
 
-    plm.add_type("read_request", ("channel", 16), ("timeout", 64))
+    plm.add_type("read_request", ("chan_sel", 24), ("timeout", 64))
 
     return plm
 

artiq/gateware/rtio/cri.py

@@ -25,7 +25,8 @@ commands = {
 
 layout = [
     ("cmd", 2, DIR_M_TO_S),
-    # 8 MSBs of chan_sel are used to select core
+    # 8  MSBs of chan_sel = routing destination
+    # 16 LSBs of chan_sel = channel within the destination
     ("chan_sel", 24, DIR_M_TO_S),
     ("timestamp", 64, DIR_M_TO_S),
 

artiq/gateware/test/drtio/test_rt_packet_repeater.py

@@ -55,7 +55,7 @@ class TestRepeater(unittest.TestCase):
                 data = field_dict["short_data"]
                 for n, te in enumerate(trailer):
                     data |= te << (n*nwords*8 + short_data_len)
-                received.append((field_dict["channel"], field_dict["timestamp"],
+                received.append((field_dict["chan_sel"], field_dict["timestamp"],
                                  field_dict["address"], data))
 
             run_simulation(dut, [send(), pr.receive(receive)])