forked from M-Labs/artiq
RELEASE_NOTES: fix formatting
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@ -9,12 +9,12 @@ ARTIQ-6
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Highlights:
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* New hardware support:
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- Zynq SoC core devices, enabling kernels to run on 1 GHz CPU core with
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a floating-point unit for faster computations. This currently requires an external
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repository (https://git.m-labs.hk/m-labs/artiq-zynq) and only supports the ZC706.
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- Mirny 4-channel wide-band PLL/VCO-based microwave frequency synthesiser
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- Fastino 32-channel, 3MS/s per channel, 16-bit DAC EEM
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- Kasli 2.0
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- Zynq SoC core devices, enabling kernels to run on 1 GHz CPU core with a floating-point
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unit for faster computations. This currently requires an external
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repository (https://git.m-labs.hk/m-labs/artiq-zynq) and only supports the ZC706.
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- Mirny 4-channel wide-band PLL/VCO-based microwave frequency synthesiser
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- Fastino 32-channel, 3MS/s per channel, 16-bit DAC EEM
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- Kasli 2.0
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* Matrix math support on the core device.
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* Trigonometric functions and miscellaneous math library support on the core device.
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* Performance improvements:
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@ -22,7 +22,7 @@ Highlights:
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than the RTIO period
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- Improved performance for kernel RPC involving list and array.
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* Coredevice SI to mu conversions now always return valid codes, or raise a ``ValueError``.
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* Zotino now exposes ``voltage_to_mu()``
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* Zotino now exposes ``voltage_to_mu()``
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* ``ad9910``: The maximum amplitude scale factor is now ``0x3fff`` (was ``0x3ffe``
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before).
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* Dashboard:
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