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gateware/targets: remove deprecated ofifo_depth parameter

This commit is contained in:
Sebastien Bourdeauducq 2017-09-16 17:04:11 +08:00
parent e2c1d4f3d5
commit 0824e0aeae
3 changed files with 12 additions and 17 deletions
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18
artiq/gateware/targets/kc705_dds.py
View File

@ -224,24 +224,22 @@ class NIST_CLOCK(_NIST_Ions):
phy = spi.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=4, ififo_depth=4))
phy, ififo_depth=4))
for i in range(3):
phy = spi.SPIMaster(self.platform.request("spi", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=128, ififo_depth=128))
phy, ififo_depth=128))
phy = spi.SPIMaster(platform.request("sdcard_spi_33", 0))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=4, ififo_depth=4))
phy, ififo_depth=4))
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=512,
ififo_depth=4))
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
@ -299,21 +297,19 @@ class NIST_QC2(_NIST_Ions):
phy = spi.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=4, ififo_depth=4))
phy, ififo_depth=4))
for i in range(4):
phy = spi.SPIMaster(self.platform.request("spi", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=128, ififo_depth=128))
phy, ififo_depth=128))
for backplane_offset in range(2):
phy = dds.AD9914(
platform.request("dds", backplane_offset), 12, onehot=True)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=512,
ififo_depth=4))
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)

4
artiq/gateware/targets/kc705_sma_spi.py
View File

@ -101,12 +101,12 @@ class SMA_SPI(_NIST_Ions):
phy = spi.SPIMaster(ams101_dac)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=4, ififo_depth=4))
phy, ififo_depth=4))
phy = spi.SPIMaster(self.platform.request("sma_spi"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=128, ififo_depth=128))
phy, ififo_depth=128))
self.config["HAS_RTIO_LOG"] = None
self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)

3
artiq/gateware/targets/phaser.py
View File

@ -213,8 +213,7 @@ class Phaser(MiniSoC, AMPSoC):
sysref_pads = platform.request("ad9154_sysref")
phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
ofifo_depth=2))
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32))
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
rtio_channels.extend(rtio.Channel.from_phy(phy)