forked from M-Labs/artiq
rtio/sed/LaneDistributor: support specifying existing CRI
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1cb05f3ed5
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064503f224
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@ -7,18 +7,19 @@ from artiq.gateware.rtio.sed import layouts
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__all__ = ["LaneDistributor"]
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__all__ = ["LaneDistributor"]
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# CRI write happens in 3 cycles:
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# CRI write happens in 3 cycles:
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# 1. set timestamp
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# 1. set timestamp
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# 2. set other payload elements and issue write command
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# 2. set other payload elements and issue write command
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# 3. check status
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# 3. check status
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class LaneDistributor(Module):
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class LaneDistributor(Module):
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def __init__(self, lane_count, seqn_width, layout_payload, fine_ts_width, enable_spread=True):
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def __init__(self, lane_count, seqn_width, layout_payload, fine_ts_width, enable_spread=True, interface=None):
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if lane_count & (lane_count - 1):
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if lane_count & (lane_count - 1):
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raise NotImplementedError("lane count must be a power of 2")
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raise NotImplementedError("lane count must be a power of 2")
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self.cri = cri.Interface()
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if interface is None:
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interface = cri.Interface()
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self.cri = interface
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self.minimum_coarse_timestamp = Signal(64-fine_ts_width)
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self.minimum_coarse_timestamp = Signal(64-fine_ts_width)
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self.lane_io = [Record(layouts.fifo_ingress(seqn_width, layout_payload))
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self.lane_io = [Record(layouts.fifo_ingress(seqn_width, layout_payload))
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for _ in range(lane_count)]
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for _ in range(lane_count)]
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