2014-09-12 15:28:02 +08:00
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from artiq.language.core import *
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2014-09-30 19:32:11 +08:00
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from artiq.devices.runtime_exceptions import RTIOSequenceError
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2014-09-12 15:28:02 +08:00
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2014-09-15 22:48:22 +08:00
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class _RTIOBase(AutoContext):
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2014-09-12 15:28:02 +08:00
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parameters = "channel"
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def build(self):
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self.previous_timestamp = int64(0)
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self.previous_value = 0
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kernel_attr = "previous_timestamp previous_value"
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2014-09-15 22:48:22 +08:00
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@kernel
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def _set_oe(self, oe):
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syscall("rtio_oe", self.channel, oe)
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2014-09-12 15:28:02 +08:00
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@kernel
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def _set_value(self, value):
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2014-09-30 19:32:11 +08:00
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if now() < self.previous_timestamp:
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raise RTIOSequenceError
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2014-09-12 15:28:02 +08:00
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if self.previous_value != value:
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if self.previous_timestamp == now():
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syscall("rtio_replace", now(), self.channel, value)
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else:
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syscall("rtio_set", now(), self.channel, value)
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self.previous_timestamp = now()
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self.previous_value = value
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2014-09-15 22:48:22 +08:00
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class RTIOOut(_RTIOBase):
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2014-09-30 16:42:07 +08:00
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"""RTIO output driver.
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2014-09-30 18:10:40 +08:00
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Configures the corresponding RTIO channel as output on the core device and
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provides functions to set its level.
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2014-09-30 16:42:07 +08:00
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This driver supports zero-length transition suppression. For example, if
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two pulses are emitted back-to-back with no delay between them, they will
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be merged into a single pulse with a duration equal to the sum of the
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durations of the original pulses.
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:param core: core device
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:param channel: channel number
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"""
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2014-09-15 22:48:22 +08:00
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def build(self):
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_RTIOBase.build(self)
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self._set_oe(1)
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2014-09-12 15:28:02 +08:00
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@kernel
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def sync(self):
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2014-09-30 16:42:07 +08:00
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"""Busy-waits until all programmed level switches have been effected.
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This function is useful to synchronize CPU-controlled devices (such as
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the AD9858 DDS bus) with related RTIO controls (such as RF switches at
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the output of the DDS).
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"""
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2014-09-12 15:28:02 +08:00
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syscall("rtio_sync", self.channel)
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@kernel
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def on(self):
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2014-09-30 16:42:07 +08:00
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"""Sets the output to a logic high state.
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"""
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2014-09-12 15:28:02 +08:00
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self._set_value(1)
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@kernel
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def off(self):
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2014-09-30 16:42:07 +08:00
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"""Sets the output to a logic low state.
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"""
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2014-09-12 15:28:02 +08:00
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self._set_value(0)
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@kernel
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def pulse(self, duration):
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2014-09-30 16:42:07 +08:00
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"""Pulses the output high for the specified duration.
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"""
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2014-09-12 15:28:02 +08:00
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self.on()
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delay(duration)
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self.off()
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2014-09-13 19:37:57 +08:00
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2014-09-30 16:42:07 +08:00
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class RTIOIn(_RTIOBase):
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"""RTIO input driver.
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2014-09-30 18:10:40 +08:00
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Configures the corresponding RTIO channel as input on the core device and
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provides functions to analyze the incoming signal, with real-time gating
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to prevent overflows.
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2014-09-30 16:42:07 +08:00
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:param core: core device
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:param channel: channel number
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"""
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2014-09-15 22:48:22 +08:00
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def build(self):
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_RTIOBase.build(self)
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self._set_oe(0)
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2014-09-13 19:37:57 +08:00
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@kernel
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2014-09-30 16:42:07 +08:00
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def gate_rising(self, duration):
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"""Register rising edge events for the specified duration.
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"""
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2014-09-15 22:48:22 +08:00
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self._set_value(1)
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delay(duration)
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self._set_value(0)
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@kernel
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2014-09-30 16:42:07 +08:00
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def gate_falling(self, duration):
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"""Register falling edge events for the specified duration.
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"""
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2014-09-15 22:48:22 +08:00
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self._set_value(2)
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delay(duration)
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self._set_value(0)
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@kernel
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2014-09-30 16:42:07 +08:00
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def gate_both(self, duration):
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"""Register both rising and falling edge events for the specified
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duration.
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"""
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2014-09-15 22:48:22 +08:00
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self._set_value(3)
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delay(duration)
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self._set_value(0)
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2014-09-13 19:37:57 +08:00
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@kernel
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2014-09-30 16:42:07 +08:00
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def count(self):
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"""Poll the RTIO input during all the previously programmed gate
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openings, and returns the number of registered events.
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"""
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2014-09-15 22:48:22 +08:00
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count = 0
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while syscall("rtio_get", self.channel) >= 0:
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count += 1
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return count
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