cargo fmt

Signed-off-by: Jonathan Coates <jonathan.coates@oxionics.com>

flake.lock

@@ -11,11 +11,11 @@
         "src-pythonparser": "src-pythonparser"
       },
       "locked": {
-        "lastModified": 1731734344,
-        "narHash": "sha256-2vLRo9D5wDs5FArpc2pOfuKFrhnqIKjtZos88VJahhc=",
+        "lastModified": 1734418848,
+        "narHash": "sha256-FiK84edtdmpJ3FUA58XAUmDDp4oVPgupmf1CcgJ6rC0=",
         "ref": "refs/heads/master",
-        "rev": "27d54cb8f3a394b4f4adcbb3c2c9160c5bf3df47",
-        "revCount": 9049,
+        "rev": "366bb0fc59dbe4d5f544908b0f3e31f8eb19f7c1",
+        "revCount": 9121,
         "type": "git",
         "url": "https://github.com/m-labs/artiq.git"
       },
@@ -70,11 +70,11 @@
     },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1731319897,
-        "narHash": "sha256-PbABj4tnbWFMfBp6OcUK5iGy1QY+/Z96ZcLpooIbuEI=",
+        "lastModified": 1733940404,
+        "narHash": "sha256-Pj39hSoUA86ZePPF/UXiYHHM7hMIkios8TYG29kQT4g=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "dc460ec76cbff0e66e269457d7b728432263166c",
+        "rev": "5d67ea6b4b63378b9c13be21e2ec9d1afc921713",
         "type": "github"
       },
       "original": {
@@ -142,11 +142,11 @@
         ]
       },
       "locked": {
-        "lastModified": 1728371104,
-        "narHash": "sha256-PPnAyDedUQ7Og/Cby9x5OT9wMkNGTP8GS53V6N/dk4w=",
+        "lastModified": 1734267097,
+        "narHash": "sha256-aWg7XDiOlWnkXfDbKrBn9ITR46/JXfndvYHxFJ1vN78=",
         "owner": "m-labs",
         "repo": "sipyco",
-        "rev": "094a6cd63ffa980ef63698920170e50dc9ba77fd",
+        "rev": "430978ada3fefe32de01f1b884b3031e48aaef96",
         "type": "github"
       },
       "original": {
@@ -229,11 +229,11 @@
         "rust-overlay": "rust-overlay_2"
       },
       "locked": {
-        "lastModified": 1731749494,
-        "narHash": "sha256-WGigAhvVCGN5YZ1dHPyvoqAh47W1Gtph036O1aKFlLE=",
+        "lastModified": 1734668221,
+        "narHash": "sha256-X0U2yPmlsD3VLBZQyfWv8qw04Qn0qFWIONJUPPigB0U=",
         "ref": "refs/heads/master",
-        "rev": "12975de2e110d7948bf47b768559f727d0abc8fc",
-        "revCount": 655,
+        "rev": "213529cf7a50aa1b2d9ffdf575e3e38202ff9bd6",
+        "revCount": 666,
         "type": "git",
         "url": "https://git.m-labs.hk/m-labs/zynq-rs"
       },

flake.nix

@@ -10,7 +10,7 @@
     pkgs = import artiq.inputs.nixpkgs { system = "x86_64-linux"; overlays = [ (import zynq-rs.inputs.rust-overlay) ]; };
     zynqpkgs = zynq-rs.packages.x86_64-linux;
     artiqpkgs = artiq.packages.x86_64-linux;
-    llvmPackages_11 = zynq-rs.llvmPackages_11;
+    zynqRev = self.sourceInfo.rev or "unknown";
 
     rust = zynq-rs.rust;
     rustPlatform = zynq-rs.rustPlatform;
@@ -125,7 +125,9 @@
           lockFile = src/Cargo.lock;
           outputHashes = {
               "tar-no-std-0.1.8" = "sha256-xm17108v4smXOqxdLvHl9CxTCJslmeogjm4Y87IXFuM=";
-              "nalgebra-0.32.6" = "sha256-L/YudkVOtfGYoNQKBD7LMk/sMYgRDzPDdpGL5rO7G2I=";
+              "nalgebra-0.32.6" = "sha256-ZbQQZbM3A5cJ4QbujtUxkrI0/qGlI4UzfahtyQnvMZA=";
+              "core_io-0.1.0" = "sha256-0HINFWRiJx8pjMgUOL/CS336ih7SENSRh3Kah9LPRrw=";
+              "fatfs-0.3.6" = "sha256-Nz9hCq/1YgSXF8ltJ5ZawV0Hc8WV44KNK0tJdVnNb4U=";
             };
         };
 
@@ -133,12 +135,13 @@
           pkgs.gnumake
           (pkgs.python3.withPackages(ps: [ ps.jsonschema artiqpkgs.migen migen-axi artiqpkgs.misoc artiqpkgs.artiq ]))
           zynqpkgs.cargo-xbuild
-          llvmPackages_11.llvm
-          llvmPackages_11.clang-unwrapped
+          pkgs.llvmPackages_13.llvm
+          pkgs.llvmPackages_13.clang-unwrapped
         ];
         buildPhase = ''
+          export ZYNQ_REV=${zynqRev}
           export XARGO_RUST_SRC="${rust}/lib/rustlib/src/rust/library"
-          export CLANG_EXTRA_INCLUDE_DIR="${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include"
+          export CLANG_EXTRA_INCLUDE_DIR="${pkgs.llvmPackages_13.clang-unwrapped.lib}/lib/clang/13.0.1/include"
           export CARGO_HOME=$(mktemp -d cargo-home.XXX)
           export ZYNQ_RS=${zynq-rs}
           make TARGET=${target} GWARGS="${if json == null then "-V ${variant}" else json}" ${fwtype}
@@ -164,6 +167,7 @@
           ];
         }
         ''
+          export ZYNQ_REV=${zynqRev}
           python ${./src/gateware}/${target}.py -g build ${if json == null then "-V ${variant}" else json}
           mkdir -p $out $out/nix-support
           cp build/top.bit $out
@@ -372,8 +376,8 @@
       name = "artiq-zynq-dev-shell";
       buildInputs = with pkgs; [
         rust
-        llvmPackages_11.llvm
-        llvmPackages_11.clang-unwrapped
+        llvmPackages_13.llvm
+        llvmPackages_13.clang-unwrapped
         gnumake
         cacert
         zynqpkgs.cargo-xbuild
@@ -386,8 +390,9 @@
         binutils-arm
         pre-commit
       ];
+      ZYNQ_REV="${zynqRev}";
       XARGO_RUST_SRC = "${rust}/lib/rustlib/src/rust/library";
-      CLANG_EXTRA_INCLUDE_DIR = "${llvmPackages_11.clang-unwrapped.lib}/lib/clang/11.1.0/include";
+      CLANG_EXTRA_INCLUDE_DIR = "${pkgs.llvmPackages_13.clang-unwrapped.lib}/lib/clang/13.0.1/include";
       ZYNQ_RS = "${zynq-rs}";
       OPENOCD_ZYNQ = "${zynq-rs}/openocd";
       SZL = "${zynqpkgs.szl}";

src/Cargo.lock

@@ -58,9 +58,9 @@ version = "0.0.0"
 
 [[package]]
 name = "byteorder"
-version = "1.4.3"
+version = "1.3.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "14c189c53d098945499cdfa7ecc63567cf3886b3332b312a5b4585d8d3a6a610"
+checksum = "60f0b0d4c0a382d2734228fd12b5a6b5dac185c60e938026fd31b265b94f9bd2"
 
 [[package]]
 name = "cc"
@@ -82,18 +82,14 @@ checksum = "baf1de4339761588bc0619e3cbc0120ee582ebb74b53b4efbf79117bd2da40fd"
 
 [[package]]
 name = "compiler_builtins"
-version = "0.1.39"
+version = "0.1.49"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "3748f82c7d366a0b4950257d19db685d4958d2fa27c6d164a3f069fec42b748b"
+checksum = "20b1438ef42c655665a8ab2c1c6d605a305f031d38d9be689ddfef41a20f3aa2"
 
 [[package]]
 name = "core_io"
-version = "0.1.20210325"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "97f8932064288cc79feb4d343a399d353a6f6f001e586ece47fe518a9e8507df"
-dependencies = [
- "rustc_version",
-]
+version = "0.1.0"
+source = "git+https://git.m-labs.hk/M-Labs/rs-core_io.git?rev=e9d3edf027#e9d3edf0272502b0dd6c26e8a4869c2912657615"
 
 [[package]]
 name = "crc"
@@ -141,9 +137,8 @@ dependencies = [
 
 [[package]]
 name = "fatfs"
-version = "0.3.5"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e18f80a87439240dac45d927fd8f8081b6f1e34c03e97271189fa8a8c2e96c8f"
+version = "0.3.6"
+source = "git+https://git.m-labs.hk/M-Labs/rust-fatfs.git?rev=4b5e420084#4b5e420084fd1c4a9c105680b687523909b6469c"
 dependencies = [
  "bitflags",
  "byteorder",
@@ -373,9 +368,9 @@ checksum = "822add9edb1860698b79522510da17bef885171f75aa395cff099d770c609c24"
 
 [[package]]
 name = "log"
-version = "0.4.17"
+version = "0.4.14"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "abb12e687cfb44aa40f41fc3978ef76448f9b6038cad6aef4259d3c095a2382e"
+checksum = "51b9bbe6c47d51fc3e1a9b945965946b4c44142ab8792c50835a980d362c2710"
 dependencies = [
  "cfg-if 1.0.0",
 ]
@@ -395,7 +390,7 @@ checksum = "c75de51135344a4f8ed3cfe2720dc27736f7711989703a0b43aadf3753c55577"
 [[package]]
 name = "nalgebra"
 version = "0.32.6"
-source = "git+https://git.m-labs.hk/M-Labs/nalgebra.git?rev=dd00f9b#dd00f9b46046e0b931d1b470166db02fd29591be"
+source = "git+https://git.m-labs.hk/M-Labs/nalgebra.git?rev=ad42410ab0#ad42410ab0abb014229e3ff6bc6ccd39ca92d5d1"
 dependencies = [
  "approx",
  "num-complex",
@@ -520,6 +515,7 @@ dependencies = [
  "build_zynq",
  "byteorder",
  "core_io",
+ "crc",
  "cslice",
  "dwarf",
  "dyld",
@@ -545,15 +541,6 @@ dependencies = [
  "void",
 ]
 
-[[package]]
-name = "rustc_version"
-version = "0.1.7"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "c5f5376ea5e30ce23c03eb77cbe4962b988deead10910c372b226388b594c084"
-dependencies = [
- "semver",
-]
-
 [[package]]
 name = "satman"
 version = "0.0.0"
@@ -578,12 +565,6 @@ dependencies = [
  "unwind",
 ]
 
-[[package]]
-name = "semver"
-version = "0.1.20"
-source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d4f410fedcf71af0345d7607d246e7ad15faaadd49d240ee3b24e5dc21a820ac"
-
 [[package]]
 name = "simba"
 version = "0.8.0"

src/armv7-none-eabihf.json

@@ -1,12 +1,4 @@
 {
-  "abi-blacklist": [
-    "stdcall",
-    "fastcall",
-    "vectorcall",
-    "thiscall",
-    "win64",
-    "sysv64"
-  ],
   "arch": "arm",
   "data-layout": "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64",
   "emit-debug-gdb-scripts": false,
@@ -21,7 +13,6 @@
   "os": "none",
   "panic-strategy": "abort",
   "requires-uwtable": true,
-  "force-unwind-tables": "yes",
   "relocation-model": "static",
   "target-c-int-width": "32",
   "target-endian": "little",

src/gateware/config.py

@@ -1,5 +1,15 @@
+import os
+from artiq._version import get_version
 from misoc.integration import cpu_interface
 
+
+def generate_ident(variant):
+    return "{}+{};{}".format(
+        get_version().split(".")[0],
+        os.getenv("ZYNQ_REV", default="unknown")[:8],
+        variant,
+    )
+
 def write_csr_file(soc, filename):
     with open(filename, "w") as f:
         f.write(cpu_interface.get_csr_rust(

src/gateware/ebaz4205.py

@@ -7,7 +7,7 @@ import dma
 from artiq.gateware import rtio
 from artiq.gateware.rtio.phy import spi2, ttl_simple
 from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
-from config import write_csr_file, write_mem_file, write_rustc_cfg_file
+from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
 from migen import *
 from migen.build.generic_platform import IOStandard, Misc, Pins, Subsignal
 from migen.build.platforms import ebaz4205
@@ -125,7 +125,7 @@ class EBAZ4205(SoCCore):
             "set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gmii_tx_clk_IBUF]"
         )
 
-        ident = self.__class__.__name__
+        ident = generate_ident(self.__class__.__name__)
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident)

src/gateware/kasli_soc.py

@@ -24,10 +24,10 @@ from artiq.gateware.wrpll import wrpll
 
 import dma
 import analyzer
-import acpki
+import acpki as acpki_lib
 import drtio_aux_controller
 import zynq_clocking
-from config import write_csr_file, write_mem_file, write_rustc_cfg_file
+from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
 
 eem_iostandard_dict = {
      0: "LVDS_25",
@@ -115,7 +115,7 @@ class GenericStandalone(SoCCore):
         platform.toolchain.bitstream_commands.extend([
             "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
         ])
-        ident = description["variant"]
+        ident = generate_ident(description["variant"])
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@@ -184,10 +184,10 @@ class GenericStandalone(SoCCore):
 
         if self.acpki:
             self.config["KI_IMPL"] = "acp"
-            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
-                                                         bus=self.ps7.s_axi_acp,
-                                                         user=self.ps7.s_axi_acp_user,
-                                                         evento=self.ps7.event.o)
+            self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
+                                                             bus=self.ps7.s_axi_acp,
+                                                             user=self.ps7.s_axi_acp_user,
+                                                             evento=self.ps7.event.o)
             self.csr_devices.append("rtio")
         else:
             self.config["KI_IMPL"] = "csr"
@@ -229,7 +229,7 @@ class GenericMaster(SoCCore):
         platform.toolchain.bitstream_commands.extend([
             "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
         ])
-        ident = description["variant"]
+        ident = generate_ident(description["variant"])
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@@ -349,10 +349,10 @@ class GenericMaster(SoCCore):
 
         if self.acpki:
             self.config["KI_IMPL"] = "acp"
-            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
-                                                         bus=self.ps7.s_axi_acp,
-                                                         user=self.ps7.s_axi_acp_user,
-                                                         evento=self.ps7.event.o)
+            self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
+                                                             bus=self.ps7.s_axi_acp,
+                                                             user=self.ps7.s_axi_acp_user,
+                                                             evento=self.ps7.event.o)
             self.csr_devices.append("rtio")
         else:
             self.config["KI_IMPL"] = "csr"
@@ -438,7 +438,7 @@ class GenericSatellite(SoCCore):
         platform.toolchain.bitstream_commands.extend([
             "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
         ])
-        ident = description["variant"]
+        ident = generate_ident(description["variant"])
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@@ -544,10 +544,10 @@ class GenericSatellite(SoCCore):
 
         if self.acpki:
             self.config["KI_IMPL"] = "acp"
-            self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
-                                                         bus=self.ps7.s_axi_acp,
-                                                         user=self.ps7.s_axi_acp_user,
-                                                         evento=self.ps7.event.o)
+            self.submodules.rtio = acpki_lib.KernelInitiator(self.rtio_tsc,
+                                                             bus=self.ps7.s_axi_acp,
+                                                             user=self.ps7.s_axi_acp_user,
+                                                             evento=self.ps7.event.o)
             self.csr_devices.append("rtio")
         else:
             self.config["KI_IMPL"] = "csr"

src/gateware/zc706.py

@@ -25,7 +25,7 @@ import analyzer
 import acpki
 import drtio_aux_controller
 import zynq_clocking
-from config import write_csr_file, write_mem_file, write_rustc_cfg_file
+from config import generate_ident, write_csr_file, write_mem_file, write_rustc_cfg_file
 
 class SMAClkinForward(Module):
     def __init__(self, platform):
@@ -130,7 +130,7 @@ class ZC706(SoCCore):
         platform = zc706.Platform()
         prepare_zc706_platform(platform)
 
-        ident = self.__class__.__name__
+        ident = generate_ident(self.__class__.__name__)
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@@ -203,7 +203,7 @@ class _MasterBase(SoCCore):
 
         platform = zc706.Platform()
         prepare_zc706_platform(platform)
-        ident = self.__class__.__name__
+        ident = generate_ident(self.__class__.__name__)
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
@@ -344,7 +344,7 @@ class _SatelliteBase(SoCCore):
 
         platform = zc706.Platform()
         prepare_zc706_platform(platform)
-        ident = self.__class__.__name__
+        ident = generate_ident(self.__class__.__name__)
         if self.acpki:
             ident = "acpki_" + ident
         SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)

src/libboard_artiq/Cargo.toml.tpl

@@ -20,7 +20,7 @@ build_zynq = { path = "../libbuild_zynq" }
 log = "0.4"
 log_buffer = { version = "1.2" }
 crc = { version = "1.7", default-features = false }
-core_io = { version = "0.1", features = ["collections"] }
+core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf027", features = ["collections"] }
 embedded-hal = "0.2"
 nb = "1.0"
 void = { version = "1", default-features = false }

src/libboard_artiq/src/drtioaux.rs

@@ -6,7 +6,7 @@ use io::{proto::{ProtoRead, ProtoWrite},
          Cursor};
 use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
 
-pub use crate::drtioaux_proto::Packet;
+pub use crate::drtioaux_proto::{Packet, MAX_PACKET};
 use crate::{drtioaux_proto::Error as ProtocolError, mem::mem::DRTIOAUX_MEM, pl::csr::DRTIOAUX};
 
 #[derive(Debug)]
@@ -35,6 +35,15 @@ impl From<IoError> for Error {
     }
 }
 
+pub fn copy_work_buffer(src: *mut u32, dst: *mut u32, len: isize) {
+    // fix for artiq-zynq#344
+    unsafe {
+        for i in 0..(len / 4) {
+            *dst.offset(i) = *src.offset(i);
+        }
+    }
+}
+
 pub fn reset(linkno: u8) {
     let linkno = linkno as usize;
     unsafe {
@@ -115,7 +124,9 @@ where F: FnOnce(&mut [u8]) -> Result<usize, Error> {
     unsafe {
         while (DRTIOAUX[linkno].aux_tx_read)() != 0 {}
         let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;
-        let len = f(slice::from_raw_parts_mut(ptr as *mut u8, 0x400 as usize))?;
+        let mut buf: [u8; MAX_PACKET] = [0; MAX_PACKET];
+        let len = f(&mut buf)?;
+        copy_work_buffer(buf.as_mut_ptr() as *mut u32, ptr, len as isize);
         (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
         (DRTIOAUX[linkno].aux_tx_write)(1);
         Ok(())

src/libboard_artiq/src/drtioaux_async.rs

@@ -9,8 +9,8 @@ use libboard_zynq::{time::Milliseconds, timer::GlobalTimer};
 use nb;
 use void::Void;
 
-pub use crate::drtioaux_proto::Packet;
-use crate::{drtioaux::{has_rx_error, Error},
+pub use crate::drtioaux_proto::{Packet, MAX_PACKET};
+use crate::{drtioaux::{copy_work_buffer, has_rx_error, Error},
             mem::mem::DRTIOAUX_MEM,
             pl::csr::DRTIOAUX};
 
@@ -102,7 +102,9 @@ where F: FnOnce(&mut [u8]) -> Result<usize, Error> {
     unsafe {
         let _ = block_async!(tx_ready(linkno)).await;
         let ptr = DRTIOAUX_MEM[linkno].base as *mut u32;
-        let len = f(slice::from_raw_parts_mut(ptr as *mut u8, 0x400 as usize))?;
+        let mut buf: [u8; MAX_PACKET] = [0; MAX_PACKET];
+        let len = f(&mut buf)?;
+        copy_work_buffer(buf.as_mut_ptr() as *mut u32, ptr, len as isize);
         (DRTIOAUX[linkno].aux_tx_length_write)(len as u16);
         (DRTIOAUX[linkno].aux_tx_write)(1);
         Ok(())

src/libboard_artiq/src/drtioaux_proto.rs

@@ -1,11 +1,12 @@
 use core_io::{Error as IoError, Read, Write};
 use io::proto::{ProtoRead, ProtoWrite};
 
-const MAX_PACKET: usize = 1024;
+pub const MAX_PACKET: usize = 1024;
 
 // maximum size of arbitrary payloads
 // used by satellite -> master analyzer, subkernel exceptions
-pub const SAT_PAYLOAD_MAX_SIZE: usize  = /*max size*/MAX_PACKET - /*CRC*/4 - /*packet ID*/1 - /*last*/1 - /*length*/2;
+pub const SAT_PAYLOAD_MAX_SIZE: usize = /*max size*/
+    MAX_PACKET - /*CRC*/4 - /*packet ID*/1 - /*last*/1 - /*length*/2;
 // used by DDMA, subkernel program data (need to provide extra ID and destination)
 pub const MASTER_PAYLOAD_MAX_SIZE: usize = SAT_PAYLOAD_MAX_SIZE - /*source*/1 - /*destination*/1 - /*ID*/4;
 
@@ -1268,7 +1269,8 @@ impl Packet {
             | Packet::SubkernelMessageAck { .. }
             | Packet::DmaPlaybackStatus { .. }
             | Packet::SubkernelFinished { .. }
-            | Packet::CoreMgmtDropLinkAck { .. } => false,
+            | Packet::CoreMgmtDropLinkAck { .. }
+            | Packet::InjectionRequest { .. } => false,
             _ => true,
         }
     }

src/libdwarf/src/eh.rs

@@ -85,10 +85,7 @@ unsafe fn get_ttype_entry(
         encoding | DW_EH_PE_pcrel,
         ttype_base,
     )
-    .map(|v| match v {
-        ttype_base => None,
-        ttype_entry => Some(ttype_entry as *const u8),
-    })
+    .map(|v| (v != ttype_base).then(|| v as *const u8))
 }
 
 pub unsafe fn find_eh_action(

src/libio/Cargo.toml.tpl

@@ -8,7 +8,7 @@ name = "io"
 path = "lib.rs"
 
 [dependencies]
-core_io = { version = "0.1", features = ["collections"] }
+core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf027", features = ["collections"] }
 byteorder = { version = "1.0", default-features = false, optional = true }
 
 libsupport_zynq = { path = "@@ZYNQ_RS@@/libsupport_zynq", default-features = false, features = ["alloc_core"] }

src/libio/cursor.rs

@@ -1,5 +1,6 @@
 #[cfg(feature = "alloc")]
 use alloc::vec::Vec;
+use core::arch::asm;
 
 use core_io::{Error as IoError, Read, Write};
 
@@ -47,6 +48,9 @@ impl<T: AsRef<[u8]>> Read for Cursor<T> {
         let len = buf.len().min(data.len());
         // ``copy_from_slice`` generates AXI bursts, use a regular loop instead
         for i in 0..len {
+            unsafe {
+                asm!("", options(preserves_flags, nostack, readonly));
+            }
             buf[i] = data[i];
         }
         self.pos += len;
@@ -59,6 +63,9 @@ impl Write for Cursor<&mut [u8]> {
         let data = &mut self.inner[self.pos..];
         let len = buf.len().min(data.len());
         for i in 0..len {
+            unsafe {
+                asm!("", options(preserves_flags, nostack, readonly));
+            }
             data[i] = buf[i];
         }
         self.pos += len;

src/libio/lib.rs

@@ -1,5 +1,6 @@
 #![no_std]
 #![feature(never_type)]
+#![feature(asm)]
 
 #[cfg(feature = "alloc")]
 extern crate alloc;

src/libksupport/Cargo.toml.tpl

@@ -12,7 +12,7 @@ build_zynq = { path = "../libbuild_zynq" }
 cslice = "0.3"
 log = "0.4"
 nb = "0.1"
-core_io = { version = "0.1", features = ["collections"] }
+core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf027", features = ["collections"] }
 byteorder = { version = "1.3", default-features = false }
 void = { version = "1", default-features = false }
 log_buffer = { version = "1.2" }
@@ -35,6 +35,6 @@ libboard_artiq = { path = "../libboard_artiq" }
 
 [dependencies.nalgebra]
 git = "https://git.m-labs.hk/M-Labs/nalgebra.git"
-rev = "dd00f9b"
+rev = "ad42410ab0"
 default-features = false
 features = ["libm", "alloc"]

src/libksupport/src/eh_artiq.rs

@@ -96,29 +96,35 @@ struct ExceptionBuffer {
 }
 
 static mut EXCEPTION_BUFFER: ExceptionBuffer = ExceptionBuffer {
-    uw_exceptions: [uw::_Unwind_Exception {
-        exception_class: EXCEPTION_CLASS,
-        exception_cleanup: cleanup,
-        private: [0; uw::unwinder_private_data_size],
+    uw_exceptions: [const {
+        uw::_Unwind_Exception {
+            exception_class: EXCEPTION_CLASS,
+            exception_cleanup: cleanup,
+            private: [0; uw::unwinder_private_data_size],
+        }
     }; MAX_INFLIGHT_EXCEPTIONS],
     exceptions: [None; MAX_INFLIGHT_EXCEPTIONS + 1],
     exception_stack: [-1; MAX_INFLIGHT_EXCEPTIONS + 1],
     backtrace: [(0, 0); MAX_BACKTRACE_SIZE],
     backtrace_size: 0,
-    stack_pointers: [StackPointerBacktrace {
-        stack_pointer: 0,
-        initial_backtrace_size: 0,
-        current_backtrace_size: 0,
+    stack_pointers: [const {
+        StackPointerBacktrace {
+            stack_pointer: 0,
+            initial_backtrace_size: 0,
+            current_backtrace_size: 0,
+        }
     }; MAX_INFLIGHT_EXCEPTIONS + 1],
     exception_count: 0,
 };
 
 pub unsafe extern "C" fn reset_exception_buffer() {
     trace!("reset exception buffer");
-    EXCEPTION_BUFFER.uw_exceptions = [uw::_Unwind_Exception {
-        exception_class: EXCEPTION_CLASS,
-        exception_cleanup: cleanup,
-        private: [0; uw::unwinder_private_data_size],
+    EXCEPTION_BUFFER.uw_exceptions = [const {
+        uw::_Unwind_Exception {
+            exception_class: EXCEPTION_CLASS,
+            exception_cleanup: cleanup,
+            private: [0; uw::unwinder_private_data_size],
+        }
     }; MAX_INFLIGHT_EXCEPTIONS];
     EXCEPTION_BUFFER.exceptions = [None; MAX_INFLIGHT_EXCEPTIONS + 1];
     EXCEPTION_BUFFER.exception_stack = [-1; MAX_INFLIGHT_EXCEPTIONS + 1];

src/libksupport/src/kernel/dma.rs

@@ -82,7 +82,7 @@ pub extern "C" fn dma_record_stop(duration: i64, enable_ddma: bool) {
 #[inline(always)]
 unsafe fn dma_record_output_prepare(timestamp: i64, target: i32, words: usize) {
     // See gateware/rtio/dma.py.
-    const HEADER_LENGTH: usize = /*length*/1 + /*channel*/3 + /*timestamp*/8 + /*address*/1;
+    const HEADER_LENGTH: usize = /*length*/ 1 + /*channel*/3 + /*timestamp*/8 + /*address*/1;
     let length = HEADER_LENGTH + /*data*/words * 4;
 
     let buffer = &mut RECORDER.as_mut().unwrap().buffer;

src/libksupport/src/lib.rs

@@ -1,7 +1,8 @@
 #![no_std]
+#![allow(incomplete_features)]
 #![feature(c_variadic)]
 #![feature(const_btree_new)]
-#![feature(const_in_array_repeat_expressions)]
+#![feature(inline_const)]
 #![feature(naked_functions)]
 #![feature(asm)]
 

src/libunwind/lib.rs

@@ -1,7 +1,7 @@
 #![no_std]
 #![feature(link_cfg)]
 #![feature(nll)]
-#![feature(unwind_attributes)]
+#![feature(c_unwind)]
 #![feature(static_nobundle)]
 #![cfg_attr(not(target_env = "msvc"), feature(libc))]
 

src/libunwind/libunwind.rs

@@ -77,8 +77,7 @@ pub type _Unwind_Exception_Cleanup_Fn =
     all(feature = "llvm-libunwind", any(target_os = "fuchsia", target_os = "linux")),
     link(name = "unwind", kind = "static")
 )]
-extern "C" {
-    #[unwind(allowed)]
+extern "C-unwind" {
     pub fn _Unwind_Resume(exception: *mut _Unwind_Exception) -> !;
     pub fn _Unwind_DeleteException(exception: *mut _Unwind_Exception);
     pub fn _Unwind_GetLanguageSpecificData(ctx: *mut _Unwind_Context) -> *mut c_void;
@@ -226,8 +225,7 @@ if #[cfg(not(all(target_os = "ios", target_arch = "arm")))] {
     #[cfg_attr(all(feature = "llvm-libunwind",
                    any(target_os = "fuchsia", target_os = "linux")),
                link(name = "unwind", kind = "static"))]
-    extern "C" {
-        #[unwind(allowed)]
+    extern "C-unwind" {
         pub fn _Unwind_RaiseException(exception: *mut _Unwind_Exception) -> _Unwind_Reason_Code;
         pub fn _Unwind_Backtrace(trace: _Unwind_Trace_Fn,
                                  trace_argument: *mut c_void)
@@ -238,8 +236,7 @@ if #[cfg(not(all(target_os = "ios", target_arch = "arm")))] {
     #[cfg_attr(all(feature = "llvm-libunwind",
                    any(target_os = "fuchsia", target_os = "linux")),
                link(name = "unwind", kind = "static"))]
-    extern "C" {
-        #[unwind(allowed)]
+    extern "C-unwind" {
         pub fn _Unwind_SjLj_RaiseException(e: *mut _Unwind_Exception) -> _Unwind_Reason_Code;
     }
 

src/runtime/Cargo.toml.tpl

@@ -20,7 +20,7 @@ num-derive = "0.3"
 cslice = "0.3"
 log = "0.4"
 embedded-hal = "0.2"
-core_io = { version = "0.1", features = ["collections"] }
+core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf027", features = ["collections"] }
 crc = { version = "1.7", default-features = false }
 byteorder = { version = "1.3", default-features = false }
 void = { version = "1", default-features = false }
@@ -46,4 +46,4 @@ libboard_artiq = { path = "../libboard_artiq" }
 
 [dependencies.tar-no-std]
 git = "https://git.m-labs.hk/M-Labs/tar-no-std"
-rev = "2ab6dc5"
+rev = "2ab6dc5"

src/runtime/src/comms.rs

@@ -10,15 +10,11 @@ use io::Cursor;
 #[cfg(has_drtio)]
 use ksupport::rpc;
 use ksupport::{kernel, resolve_channel_name};
-#[cfg(has_drtio)]
-use libasync::delay;
 use libasync::{smoltcp::{Sockets, TcpStream},
                task};
 use libboard_artiq::drtio_routing;
 #[cfg(feature = "target_kasli_soc")]
 use libboard_zynq::error_led::ErrorLED;
-#[cfg(has_drtio)]
-use libboard_zynq::time::Milliseconds;
 use libboard_zynq::{self as zynq,
                     smoltcp::{self,
                               iface::{EthernetInterfaceBuilder, NeighborCache},
@@ -788,7 +784,11 @@ pub fn main(timer: GlobalTimer, cfg: Config) {
     mgmt::start(
         cfg.clone(),
         restart_idle.clone(),
-        Some(mgmt::DrtioContext(aux_mutex.clone(), drtio_routing_table.clone(), timer)),
+        Some(mgmt::DrtioContext(
+            aux_mutex.clone(),
+            drtio_routing_table.clone(),
+            timer,
+        )),
     );
 
     task::spawn(async move {

src/rustfmt.toml

@@ -54,7 +54,7 @@ use_field_init_shorthand = false
 force_explicit_abi = true
 condense_wildcard_suffixes = false
 color = "Auto"
-required_version = "1.4.32"
+required_version = "1.4.37"
 unstable_features = false
 disable_all_formatting = false
 skip_children = false
@@ -65,4 +65,4 @@ report_todo = "Never"
 report_fixme = "Never"
 ignore = []
 emit_mode = "Files"
-make_backup = false
+make_backup = false

src/satman/Cargo.toml.tpl

@@ -16,7 +16,7 @@ build_zynq = { path = "../libbuild_zynq" }
 [dependencies]
 log = { version = "0.4", default-features = false }
 byteorder = { version = "1.3", default-features = false }
-core_io = { version = "0.1", features = ["collections"] }
+core_io = { git = "https://git.m-labs.hk/M-Labs/rs-core_io.git", rev = "e9d3edf027", features = ["collections"] }
 crc = { version = "1.7", default-features = false }
 cslice = "0.3"
 embedded-hal = "0.2"

src/satman/src/main.rs

@@ -1,6 +1,6 @@
 #![no_std]
 #![no_main]
-#![feature(alloc_error_handler, try_trait, never_type, panic_info_message)]
+#![feature(alloc_error_handler, never_type, panic_info_message)]
 
 #[macro_use]
 extern crate log;

src/satman/src/subkernel.rs

@@ -2,7 +2,7 @@ use alloc::{collections::BTreeMap,
             format,
             string::{String, ToString},
             vec::Vec};
-use core::{option::NoneError, slice, str};
+use core::{slice, str};
 
 use core_io::{Error as IoError, Write};
 use cslice::AsCSlice;
@@ -65,12 +65,6 @@ pub enum Error {
     DmaError(DmaError),
 }
 
-impl From<NoneError> for Error {
-    fn from(_: NoneError) -> Error {
-        Error::KernelNotFound
-    }
-}
-
 impl From<IoError> for Error {
     fn from(_value: IoError) -> Error {
         Error::SubkernelIoError
@@ -316,7 +310,7 @@ impl<'a> Manager<'_> {
                             complete: false,
                         },
                     );
-                    self.kernels.get_mut(&id)?
+                    self.kernels.get_mut(&id).ok_or_else(|| Error::KernelNotFound)?
                 } else {
                     kernel
                 }
@@ -329,7 +323,7 @@ impl<'a> Manager<'_> {
                         complete: false,
                     },
                 );
-                self.kernels.get_mut(&id)?
+                self.kernels.get_mut(&id).ok_or_else(|| Error::KernelNotFound)?
             }
         };
         kernel.library.extend(&data[0..data_len]);
@@ -396,15 +390,19 @@ impl<'a> Manager<'_> {
         if self.session.id == id && self.session.kernel_state == KernelState::Loaded {
             return Ok(());
         }
-        if !self.kernels.get(&id)?.complete {
+        if !self.kernels.get(&id).ok_or_else(|| Error::KernelNotFound)?.complete {
             return Err(Error::KernelNotFound);
         }
         self.session = Session::new(id);
         self.control.restart();
 
-        self.control
-            .tx
-            .send(kernel::Message::LoadRequest(self.kernels.get(&id)?.library.clone()));
+        self.control.tx.send(kernel::Message::LoadRequest(
+            self.kernels
+                .get(&id)
+                .ok_or_else(|| Error::KernelNotFound)?
+                .library
+                .clone(),
+        ));
         let reply = self.control.rx.recv();
         match reply {
             kernel::Message::LoadCompleted => Ok(()),