forked from M-Labs/artiq-zynq
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31936bee98
Author | SHA1 | Date |
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occheung | 31936bee98 | |
occheung | 60c347693f | |
occheung | cc5a666dc6 |
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@ -305,15 +305,6 @@ pub enum Packet {
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CoreMgmtClearLogRequest {
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CoreMgmtClearLogRequest {
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destination: u8,
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destination: u8,
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},
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},
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CoreMgmtPullLogRequest {
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destination: u8,
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},
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CoreMgmtPullLogReply {
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destination: u8,
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last: bool,
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length: u16,
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data: [u8; CORE_MGMT_PAYLOAD_MAX_SIZE],
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},
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CoreMgmtSetLogLevelRequest {
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CoreMgmtSetLogLevelRequest {
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destination: u8,
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destination: u8,
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log_level: u8,
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log_level: u8,
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@ -653,22 +644,6 @@ impl Packet {
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0xd2 => Packet::CoreMgmtClearLogRequest {
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0xd2 => Packet::CoreMgmtClearLogRequest {
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destination: reader.read_u8()?,
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destination: reader.read_u8()?,
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},
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},
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0xd3 => Packet::CoreMgmtPullLogRequest {
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destination: reader.read_u8()?,
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},
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0xd4 => {
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let destination = reader.read_u8()?;
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let last = reader.read_bool()?;
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let length = reader.read_u16()?;
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let mut data: [u8; CORE_MGMT_PAYLOAD_MAX_SIZE] = [0; CORE_MGMT_PAYLOAD_MAX_SIZE];
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reader.read_exact(&mut data[0..length as usize])?;
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Packet::CoreMgmtPullLogReply {
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destination: destination,
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last: last,
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length: length,
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data: data,
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}
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}
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0xd5 => Packet::CoreMgmtSetLogLevelRequest {
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0xd5 => Packet::CoreMgmtSetLogLevelRequest {
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destination: reader.read_u8()?,
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destination: reader.read_u8()?,
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log_level: reader.read_u8()?,
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log_level: reader.read_u8()?,
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@ -1131,22 +1106,6 @@ impl Packet {
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writer.write_u8(0xd2)?;
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writer.write_u8(0xd2)?;
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writer.write_u8(destination)?;
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writer.write_u8(destination)?;
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}
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}
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Packet::CoreMgmtPullLogRequest { destination } => {
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writer.write_u8(0xd3)?;
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writer.write_u8(destination)?;
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}
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Packet::CoreMgmtPullLogReply {
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destination,
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last,
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length,
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data,
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} => {
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writer.write_u8(0xd4)?;
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writer.write_u8(destination)?;
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writer.write_bool(last)?;
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writer.write_u16(length)?;
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writer.write_all(&data[0..length as usize])?;
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}
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Packet::CoreMgmtSetLogLevelRequest { destination, log_level } => {
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Packet::CoreMgmtSetLogLevelRequest { destination, log_level } => {
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writer.write_u8(0xd5)?;
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writer.write_u8(0xd5)?;
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writer.write_u8(destination)?;
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writer.write_u8(destination)?;
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@ -67,6 +67,9 @@ pub enum Request {
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ConfigRead = 12,
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ConfigRead = 12,
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ConfigWrite = 13,
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ConfigWrite = 13,
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ConfigRemove = 14,
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ConfigRemove = 14,
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ConfigErase = 15,
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DebugAllocator = 8,
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}
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}
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#[repr(i8)]
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#[repr(i8)]
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@ -469,6 +472,37 @@ mod remote_coremgmt {
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}
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}
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}
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}
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pub async fn config_erase(
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stream: &mut TcpStream,
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aux_mutex: &Rc<Mutex<bool>>,
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routing_table: &drtio_routing::RoutingTable,
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timer: GlobalTimer,
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linkno: u8,
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destination: u8,
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) -> Result<()> {
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let reply = drtio::aux_transact(
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aux_mutex,
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linkno,
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routing_table,
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&Packet::CoreMgmtConfigEraseRequest {
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destination: destination,
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},
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timer,
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)
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.await?;
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match reply {
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Packet::CoreMgmtAck { succeeded: true } => {
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write_i8(stream, Reply::Success as i8).await?;
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Ok(())
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}
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_ => {
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write_i8(stream, Reply::Error as i8).await?;
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Err(drtio::Error::UnexpectedReply.into())
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}
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}
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}
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pub async fn reboot(
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pub async fn reboot(
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stream: &mut TcpStream,
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stream: &mut TcpStream,
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aux_mutex: &Rc<Mutex<bool>>,
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aux_mutex: &Rc<Mutex<bool>>,
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@ -501,6 +535,38 @@ mod remote_coremgmt {
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}
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}
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}
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}
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}
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}
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pub async fn debug_allocator(
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stream: &mut TcpStream,
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aux_mutex: &Rc<Mutex<bool>>,
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routing_table: &drtio_routing::RoutingTable,
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timer: GlobalTimer,
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linkno: u8,
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destination: u8,
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) -> Result<()> {
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let reply = drtio::aux_transact(
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aux_mutex,
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linkno,
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routing_table,
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&Packet::CoreMgmtAllocatorDebugRequest {
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destination: destination,
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},
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timer,
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)
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.await?;
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match reply {
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Packet::CoreMgmtAck { succeeded: true } => {
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write_i8(stream, Reply::Success as i8).await?;
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Ok(())
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}
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_ => {
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error!("received unknown packet");
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write_i8(stream, Reply::Error as i8).await?;
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Err(drtio::Error::UnexpectedReply.into())
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}
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}
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}
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}
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}
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mod local_coremgmt {
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mod local_coremgmt {
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@ -607,6 +673,12 @@ mod local_coremgmt {
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Ok(())
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Ok(())
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}
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}
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pub async fn config_erase(stream: &mut TcpStream) -> Result<()> {
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error!("zynq device does not support config erase");
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write_i8(stream, Reply::Error as i8).await?;
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Ok(())
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}
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pub async fn reboot(stream: &mut TcpStream) -> Result<()> {
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pub async fn reboot(stream: &mut TcpStream) -> Result<()> {
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info!("rebooting");
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info!("rebooting");
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write_i8(stream, Reply::RebootImminent as i8).await?;
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write_i8(stream, Reply::RebootImminent as i8).await?;
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@ -615,6 +687,11 @@ mod local_coremgmt {
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unreachable!()
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unreachable!()
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}
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}
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pub async fn debug_allocator(_stream: &mut TcpStream) -> Result<()> {
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error!("zynq device does not support allocator debug print");
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Ok(())
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}
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}
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}
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#[cfg(has_drtio)]
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#[cfg(has_drtio)]
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@ -743,6 +820,19 @@ async fn handle_connection(
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Request::Reboot => {
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Request::Reboot => {
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process!(stream, _timer, _aux_mutex, _routing_table, _destination, reboot)
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process!(stream, _timer, _aux_mutex, _routing_table, _destination, reboot)
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}
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}
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Request::ConfigErase => {
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process!(stream, _timer, _aux_mutex, _routing_table, _destination, config_erase)
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}
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Request::DebugAllocator => {
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process!(
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stream,
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_timer,
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_aux_mutex,
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_routing_table,
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_destination,
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debug_allocator
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)
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}
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}?;
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}?;
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}
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}
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}
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}
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@ -1264,6 +1264,23 @@ fn process_aux_packet(
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}
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}
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}
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}
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}
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}
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drtioaux::Packet::CoreMgmtConfigEraseRequest {
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destination: _destination,
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} => {
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forward!(
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router,
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_routing_table,
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_destination,
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*rank,
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*self_destination,
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_repeaters,
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&packet,
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timer
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);
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error!("config erasen not supported on zynq device");
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Ok(())
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}
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drtioaux::Packet::CoreMgmtRebootRequest {
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drtioaux::Packet::CoreMgmtRebootRequest {
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destination: _destination,
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destination: _destination,
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} => {
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} => {
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@ -1284,6 +1301,23 @@ fn process_aux_packet(
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slcr::reboot();
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slcr::reboot();
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Ok(())
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Ok(())
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}
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}
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drtioaux::Packet::CoreMgmtAllocatorDebugRequest {
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destination: _destination,
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} => {
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forward!(
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router,
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_routing_table,
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_destination,
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*rank,
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*self_destination,
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_repeaters,
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&packet,
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timer
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);
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error!("debug allocator not supported on zynq device");
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Ok(())
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}
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p => {
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p => {
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warn!("received unexpected aux packet: {:?}", p);
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warn!("received unexpected aux packet: {:?}", p);
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