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530 Commits

Author SHA1 Message Date
pca006132 d5a91a7697 updated zynq-rs for more CPU options 2020-09-04 16:43:07 +08:00
pca006132 5da76f2abb enabled cpu program flow prediction 2020-09-04 13:25:17 +08:00
pca006132 5e4bf8bbf7 runtime/comms: Faster RPC alloc 
We do busy polling for some time before doing await, for small
allocations we could avoid the context switching and reduce the latency.
 2020-09-03 16:58:44 +08:00
pca006132 cdc8ad8aee runtime/kernel/control: fixed memory leak 2020-09-03 16:51:51 +08:00
pca006132 1931957bc0 Updated cargoSha256 2020-09-02 10:15:52 +08:00
pca006132 805f1d4eff runtime: increased heap size 2020-09-02 10:15:52 +08:00
pca006132 ae07c05db4 runtime: optimize for speed and fix deadlock 
The previous method of taking the channel could cause deadlock, we now
use semaphore to signal if the channel is available instead of busy
polling the mutex.
 2020-09-02 10:15:52 +08:00
Sebastien Bourdeauducq fc285fcd13 remote_run: fix pure mode 2020-09-01 17:27:29 +08:00
Sebastien Bourdeauducq b0706f470d runtime: set default log level to Info 2020-09-01 17:11:21 +08:00
pca006132 6ede148810 Updated build scripts 2020-09-01 15:57:20 +08:00
pca006132 ccf8ae5b5d szl: implemented #96 
SZL no longer do self-extraction for runtime binary, it would boot from
SD/ethernet depending on the boot mode settings.
This allows a larger runtime binary, so we can optimize for speed in the
runtime firmware for better performance, and allow more features to be
added later.
 2020-09-01 15:57:20 +08:00
pca006132 653d143784 updated cargoSha256 2020-09-01 15:49:46 +08:00
pca006132 050b2457a4 runtime/main: removed bitstream loading code 2020-09-01 15:43:54 +08:00
pca006132 eb78e4e2da libconfig: refactored load_pl into bootgen 
Now allows loading firmware.
 2020-09-01 14:48:19 +08:00
pca006132 afecc83ecf libconfig/net_settings: made ipv6 optional feature 
This is to prepare for szl, which cannot use ipv6 due to memory
limitation.
 2020-09-01 14:48:19 +08:00
pca006132 04437e876c libconfig/load_pl: added alignment for devc buffer 
According to the TRM, the buffer should be 64B aligned.
Without the alignment would cause failure for the DMA transaction.
It seems that the allocator would give some alignment, but to be more
correct we should specify that with the alloc interface.
 2020-09-01 14:48:19 +08:00
pca006132 42f94487cf split config code into libconfig 2020-09-01 14:48:09 +08:00
pca006132 d474cf58a5 runtime/rpc: optimizations for list and arrays 
Requires https://github.com/m-labs/artiq/pull/1510
This is the commit producing the result in the table.
 2020-08-26 13:47:41 +08:00
pca006132 71427f8ec8 runtime/proto_async: simplify functions 
And the compiler can use its intrinsic for byte rev.
 2020-08-26 13:46:51 +08:00
Sebastien Bourdeauducq d6ab23de1f xbuild -> cargo-xbuild 2020-08-25 17:39:42 +08:00
Sebastien Bourdeauducq 949adbd90a cargo-xbuild: cleanup 2020-08-25 16:59:57 +08:00
Sebastien Bourdeauducq 49689dedf1 update cargosha256 2020-08-25 16:25:27 +08:00
Sebastien Bourdeauducq 538c012bc4 use new repos location for compiler-builtins-zynq 2020-08-25 16:24:30 +08:00
pca006132 ba162b3997 Fix pure build 2020-08-25 14:51:39 +08:00
pca006132 321a8e1522 runtime/kernel/core1: reset rtio after interrupted 2020-08-25 14:51:39 +08:00
pca006132 0fb278f7cb runtime/kernel/core1: allows getting backtrace when kernel is not loaded 2020-08-25 14:51:39 +08:00
pca006132 fa187fb37a runtime/kernel: use mutable static for shared channel 
Mutex would prevent restart if we failed while waiting for RPC.
 2020-08-25 14:51:39 +08:00
pca006132 e592efb2b8 enabled L2 cache and optimized ethernet 2020-08-25 14:51:39 +08:00
Sebastien Bourdeauducq 2faf74f708 Revert "drop FSBL" 
Gitea issue #94

This reverts commit 67ff3c36e2.
 2020-08-25 10:49:00 +08:00
Astro bb35d6b46a default.nix: update cargosha256 2020-08-17 19:21:25 +02:00
Astro 760f46a115 update dependencies 2020-08-17 19:17:42 +02:00
David Nadlinger 6ccd0cb389 runtime/kernel: Expose libm::atanh 2020-08-09 20:06:09 +01:00
David Nadlinger 63250240d2 runtime/kernel: Expose __powidf2 2020-08-09 19:17:38 +01:00
David Nadlinger 9f898dd2b8 runtime/rpc: Support new TArray layout (ndarrays) 
This is a port of the respective commit in the main ARTIQ
repository.
 2020-08-09 19:17:38 +01:00
pca006132 7342736124 szl: reduced binary size. 
* Compiled unlzma with -Oz and enable LTO.
* Changed one unwrap to manual handling to remove fmt code.
* Implemented custom panic handler with minimal code.
 2020-08-07 13:25:16 +08:00
Sebastien Bourdeauducq 3a8a025d5f update dependencies, zc706 -> zynq-rs 2020-08-06 20:33:23 +08:00
Sebastien Bourdeauducq 2f6310f8bd cleanup 2020-08-06 20:26:48 +08:00
Sebastien Bourdeauducq 8dabc8e6fd runtime: remove access to obsolete i_overflow_reset CSR 2020-08-06 20:23:36 +08:00
Sebastien Bourdeauducq 1eeee43d64 acpki: implement input interface 2020-08-06 18:15:34 +08:00
pca006132 0354699ae3 runtime/kernel/dma: fixed missing end of buffer marker. 
The DMA transfer would halt before.
 2020-08-06 14:00:20 +08:00
Sebastien Bourdeauducq 7873565917 runtime: expose libm tan 2020-08-06 11:45:41 +08:00
pca006132 05e1614313 runtime/kernel: fixed duration bug. 
Fixes #89.
 2020-08-06 11:12:24 +08:00
Sebastien Bourdeauducq 323191b9fc runtime: expose more libm functions 2020-08-06 10:32:20 +08:00
Sebastien Bourdeauducq 2f7cc6fc38 tune compiler optimizations 2020-08-06 10:32:20 +08:00
pca006132 5becf0af0a runtime/kernel: fixed memory corruption for cache and DMA. 2020-08-06 10:29:31 +08:00
pca006132 e7752a3d6d runtime/kernel: fixes core0 memory leak. 
Fixes #85
 2020-08-06 09:39:49 +08:00
Sebastien Bourdeauducq 984bb08d27 Makefile: optimize 2020-08-05 19:14:18 +08:00
Sebastien Bourdeauducq de2d7ecf48 typo 2020-08-05 18:52:08 +08:00
pca006132 c85e85aa6d runtime/logger: use blocking wait. 
Fixes #84 using the first solution.

If the performance is considered too slow,
we can do the second option later.
 2020-08-05 18:51:27 +08:00
pca006132 4b6c5d5679 runtime/kernel: store DMA and cache buffer on core0. 
Closes #77.
 2020-08-05 15:33:40 +08:00