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751 Commits 10 Branches 0 Tags 3.1 MiB
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751 Commits

Author SHA1 Message Date
morgan 43e4527392 fix kasli-soc demo compilation warning 2023-10-25 11:45:13 +08:00
Sebastien Bourdeauducq a08a42c954 flake: update dependencies 2023-10-20 17:46:37 +08:00
mwojcik 0a3bfc9a61 subkernel: separate tags and data 2023-10-18 12:03:43 +08:00
Egor Savkin d3fbfd75b0 Fix grabber build and warning 
Signed-off-by: Egor Savkin <es@m-labs.hk>
 2023-10-18 11:24:43 +08:00
Egor Savkin b768d5648c Add grabber module 
Signed-off-by: Egor Savkin <es@m-labs.hk>
 2023-10-16 14:35:20 +08:00
Sebastien Bourdeauducq 812aea33b3 rustfmt 2023-10-11 17:56:30 +08:00
linuswck 136e24f597 kasli-soc: Add BUFG to the IBUFGDS for MMCM CLKIN1 
- Fix Vivado Compilation Error [DRC REQP-119]
- MMCME2_ADV CLKIN1 and CLKIN2 are now driven from the same source type (BUFG)
 2023-10-11 16:45:26 +08:00
Sebastien Bourdeauducq 0f050844cf flake: update dependencies 2023-10-11 16:41:54 +08:00
linuswck a4d1be00c0 Firmware: Add drtio_eem.rs support 
- Port from Artiq repo
- Initialize the drtio_eem on main, rtio_clocking
- Driver for eem_transceiver
 2023-10-10 11:22:05 +08:00
linuswck b15322b6ba kasli_soc: Add support for shuttler on gateware 
- Port from artiq repo
- Add EEM_DRTIO gateware
 2023-10-10 11:22:05 +08:00
linuswck 8fd1306145 zynq_clocking: Add sys5x, 208MHz CLK & IDELAYCTRL 
- Port from artiq repo
- Generate sys5x for for EEM Serdes, 208MHz REF Clock for IDELAYCTRL
- Add IDELAYCTRL for IDEALYE2 in EEM Serdes
 2023-10-10 11:21:34 +08:00
Sebastien Bourdeauducq a28a819b18 add manifests target to PHONY 2023-10-09 18:29:53 +08:00
Sebastien Bourdeauducq 3f414278e2 cleanup 2023-10-09 18:28:20 +08:00
Sebastien Bourdeauducq e5aafad60d force cargo to use our copy of zynq-rs 2023-10-09 18:27:58 +08:00
mwojcik b9a0bcabeb ksupport: fix build on acpki variants 2023-10-09 17:10:45 +08:00
mwojcik 8eb359ee42 cargo fmt 2023-10-09 11:50:47 +08:00
mwojcik 7263862fd8 satellite: support optional args 2023-10-09 11:42:51 +08:00
mwojcik 29cc0a6e28 ddma/subkernel: fix wrong destination reported 2023-10-09 11:42:51 +08:00
mwojcik 616c40429e satellite: process kernel requests more often 2023-10-09 11:42:51 +08:00
mwojcik 3ea8147966 subkernel: send async statuses when requested 2023-10-09 11:42:51 +08:00
mwojcik cb79c12284 satellite: support subkernels 2023-10-09 11:42:51 +08:00
mwojcik 623cc7b79e libkernel -> ksupport 2023-10-09 11:42:51 +08:00
mwojcik 49205eea17 satellite gateware: add kernel rtio to cri 2023-10-09 11:36:23 +08:00
mwojcik 6885c618b5 move kernel-related code to separate library 2023-10-09 11:36:23 +08:00
mwojcik c696fd826f master: support optional args 2023-10-09 10:35:47 +08:00
mwojcik 4b3c9a3d08 rtio_mgt: remove support for async messages 2023-10-09 10:35:47 +08:00
mwojcik 779aea7c6a check subkernel exceptions only when awaited 2023-10-09 10:35:03 +08:00
mwojcik 6785ca2c85 subkernel: port master support 2023-10-09 10:35:03 +08:00
Sebastien Bourdeauducq cded04e2d6 flake: update dependencies 2023-10-09 10:25:46 +08:00
sven-oxionics 656cbf4546 kasli_soc: use sed_lanes value from HW description 
https://github.com/m-labs/artiq/pull/1745 added a field for setting the number of SED lanes to the HW description. This commit makes it so that the setting is used for Kasli Soc as well.
 2023-10-06 15:37:56 +01:00
mwojcik ecd4ca333c rtio_clocking: inform the user if PLL is bypassed 2023-10-06 16:27:25 +08:00
mwojcik ae3099dd8e kasli_soc: support 100MHz clock 2023-10-06 16:27:25 +08:00
mwojcik 2b9542c80b flake: expose 100mhz for zc706 2023-10-06 15:26:05 +08:00
mwojcik 49810da188 runtime: wait longer for PLL lock 2023-10-05 12:17:43 +08:00
mwojcik e451598a06 satman: fix dma reporting wrong destination 2023-09-22 10:29:48 +08:00
mwojcik f4ceca464f drtio: change async messages to sync 2023-09-21 14:18:25 +08:00
morgan f3dcd53086 firmware: fix zc706 compilation warnings 
Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
 2023-09-11 15:21:56 +08:00
morgan b3856e879b refactor `write_rustc_cfg_file()` 2023-09-11 11:48:19 +08:00
morgan 1ccae0d442 consolidate all `write..file()` into `config.py` 2023-09-11 11:48:19 +08:00
morgan 2c19f4ac31 replace rustc_cfg[ ] & change write_rustc_cfg_file 2023-09-11 11:48:19 +08:00
Sebastien Bourdeauducq b23c822ad2 flake: fix cargo hash 2023-09-07 19:04:44 +08:00
Sebastien Bourdeauducq 85ecff2cc1 cargo: update zynq-rs 2023-09-07 19:01:36 +08:00
Sebastien Bourdeauducq 3a305c8cac Revert "cargo: update dependencies" 
This reverts commit 38b0799bb0.
 2023-09-07 19:00:16 +08:00
Sebastien Bourdeauducq 38b0799bb0 cargo: update dependencies 2023-09-07 18:54:30 +08:00
Sebastien Bourdeauducq b87ec32438 cargo: update dependencies 2023-09-07 18:52:16 +08:00
morgan 615f2e3d37 remove misleading 'Actively' from docs at main.rs 2023-09-06 10:53:26 +08:00
Sebastien Bourdeauducq 37df7fd45b cargo fmt 2023-08-30 16:14:35 +08:00
Sebastien Bourdeauducq c9b574f5c7 flake: update dependencies 2023-08-30 15:43:04 +08:00
morgan 2ac7eedec1 firmware: fix compilation without virtual LEDs 
Co-authored-by: morgan <mc@m-labs.hk>
Co-committed-by: morgan <mc@m-labs.hk>
 2023-08-30 15:33:44 +08:00
MorganTL c61017fbe6 fix compiling error when cfg has has_rtio_moninj 2023-08-30 15:32:09 +08:00