forked from M-Labs/artiq-zynq
WRPLL: replace PI controller with new filter
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285b02c4b1
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@ -335,14 +335,34 @@ pub mod wrpll {
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const COUNTER_WIDTH: u32 = 24;
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const DIV_WIDTH: u32 = 2;
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const KP: i32 = 6;
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const KI: i32 = 2;
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// y[n] = b0*x[n] + b1*x[n-1] + b2*x[n-2] - a1*y[n-1] - a2*y[n-2]
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struct FilterParameters {
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pub b0: f64,
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pub b1: f64,
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pub b2: f64,
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pub a1: f64,
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pub a2: f64,
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}
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const LPF: FilterParameters = FilterParameters {
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b0: 0.07209205036273991,
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b1: 0.14418410072547982,
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b2: 0.07209205036273991,
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a1: -0.6114078511562919,
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a2: -0.10022394739274834,
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};
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static mut H_ADPLL1: i32 = 0;
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static mut H_ADPLL2: i32 = 0;
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static mut PERIOD_ERR1: i32 = 0;
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static mut PERIOD_ERR2: i32 = 0;
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static mut M_ADPLL1: i32 = 0;
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static mut M_ADPLL2: i32 = 0;
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static mut PHASE_ERR1: i32 = 0;
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static mut PHASE_ERR2: i32 = 0;
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static mut BASE_ADPLL: i32 = 0;
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static mut H_LAST_ADPLL: i32 = 0;
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static mut LAST_PERIOD_ERR: i32 = 0;
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static mut M_LAST_ADPLL: i32 = 0;
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static mut LAST_PHASE_ERR: i32 = 0;
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#[derive(Clone, Copy)]
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pub enum ISR {
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@ -470,10 +490,14 @@ pub mod wrpll {
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fn reset_plls(timer: &mut GlobalTimer) -> Result<(), &'static str> {
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unsafe {
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H_LAST_ADPLL = 0;
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LAST_PERIOD_ERR = 0;
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M_LAST_ADPLL = 0;
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LAST_PHASE_ERR = 0;
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H_ADPLL1 = 0;
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H_ADPLL2 = 0;
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PERIOD_ERR1 = 0;
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PERIOD_ERR2 = 0;
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M_ADPLL1 = 0;
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M_ADPLL2 = 0;
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PHASE_ERR1 = 0;
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PHASE_ERR2 = 0;
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}
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set_adpll(i2c::DCXO::Main, 0)?;
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set_adpll(i2c::DCXO::Helper, 0)?;
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@ -517,11 +541,14 @@ pub mod wrpll {
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fn helper_pll() -> Result<(), &'static str> {
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let period_err = tag_collector::get_period_error();
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unsafe {
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// Based on https://hackmd.io/IACbwcOTSt6Adj3_F9bKuw?view#Integral-wind-up-and-output-limiting
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let adpll = H_LAST_ADPLL + (KP + KI) * period_err - KP * LAST_PERIOD_ERR;
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let adpll = ((LPF.b0 * period_err as f64) + (LPF.b1 * PERIOD_ERR1 as f64) + (LPF.b2 * PERIOD_ERR2 as f64)
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- (LPF.a1 * H_ADPLL1 as f64)
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- (LPF.a2 * H_ADPLL2 as f64)) as i32;
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set_adpll(i2c::DCXO::Helper, BASE_ADPLL + adpll)?;
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H_LAST_ADPLL = adpll;
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LAST_PERIOD_ERR = period_err;
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H_ADPLL2 = H_ADPLL1;
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PERIOD_ERR2 = PERIOD_ERR1;
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H_ADPLL1 = adpll;
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PERIOD_ERR1 = period_err;
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};
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Ok(())
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}
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@ -529,11 +556,14 @@ pub mod wrpll {
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fn main_pll() -> Result<(), &'static str> {
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let phase_err = tag_collector::get_phase_error();
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unsafe {
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// Based on https://hackmd.io/IACbwcOTSt6Adj3_F9bKuw?view#Integral-wind-up-and-output-limiting
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let adpll = M_LAST_ADPLL + (KP + KI) * phase_err - KP * LAST_PHASE_ERR;
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let adpll = ((LPF.b0 * phase_err as f64) + (LPF.b1 * PHASE_ERR1 as f64) + (LPF.b2 * PHASE_ERR2 as f64)
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- (LPF.a1 * M_ADPLL1 as f64)
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- (LPF.a2 * M_ADPLL2 as f64)) as i32;
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set_adpll(i2c::DCXO::Main, BASE_ADPLL + adpll)?;
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M_LAST_ADPLL = adpll;
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LAST_PHASE_ERR = phase_err;
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M_ADPLL2 = M_ADPLL1;
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PHASE_ERR2 = PHASE_ERR1;
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M_ADPLL1 = adpll;
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PHASE_ERR1 = phase_err;
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};
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Ok(())
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}
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