forked from M-Labs/artiq-zynq
Gateware: kasli_soc WRPLL setup
kasli_soc: use enable_wrpll from json to switch from si5324 to si549 kasli_soc: add wrpll for all variants kasli_soc: add gtx & main tag nFIQ for all variants kasli_soc: add clk_synth_se for master & satellite kasli_soc: add wrpll_refclk for runtime kasli_soc: add skewtester for satman kasli_soc: add WRPLL_REF_CLK config for firmware
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@ -26,6 +26,7 @@ import analyzer
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import acpki
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import drtio_aux_controller
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import zynq_clocking
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import wrpll
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from config import write_csr_file, write_mem_file, write_rustc_cfg_file
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eem_iostandard_dict = {
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@ -108,6 +109,7 @@ class GenericStandalone(SoCCore):
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def __init__(self, description, acpki=False):
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self.acpki = acpki
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clk_freq = description["rtio_frequency"]
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with_wrpll = description["enable_wrpll"]
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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@ -119,13 +121,6 @@ class GenericStandalone(SoCCore):
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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self.config["HW_REV"] = description["hw_rev"]
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self.submodules += SMAClkinForward(self.platform)
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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clk_synth = platform.request("cdr_clk_clean_fabric")
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clk_synth_se = Signal()
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clk_synth_se_buf = Signal()
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@ -149,6 +144,23 @@ class GenericStandalone(SoCCore):
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self.crg = self.ps7 # HACK for eem_7series to find the clock
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self.crg.cd_sys = self.sys_crg.cd_sys
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if with_wrpll:
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self.submodules.wrpll_refclk = wrpll.SMAFrequencyMultiplier(platform.request("sma_clkin"))
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self.submodules.wrpll = wrpll.WRPLL(
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platform=self.platform,
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cd_ref=self.wrpll_refclk.cd_ref,
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main_clk_se=clk_synth_se)
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self.csr_devices.append("wrpll_refclk")
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self.csr_devices.append("wrpll")
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self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
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self.config["HAS_SI549"] = None
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self.config["WRPLL_REF_CLK"] = "SMA_CLKIN"
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else:
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self.submodules += SMAClkinForward(self.platform)
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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if has_grabber:
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@ -207,6 +219,7 @@ class GenericStandalone(SoCCore):
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class GenericMaster(SoCCore):
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def __init__(self, description, acpki=False):
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clk_freq = description["rtio_frequency"]
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with_wrpll = description["enable_wrpll"]
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has_drtio_over_eem = any(peripheral["type"] == "shuttler" for peripheral in description["peripherals"])
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self.acpki = acpki
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@ -222,8 +235,6 @@ class GenericMaster(SoCCore):
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self.config["HW_REV"] = description["hw_rev"]
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self.submodules += SMAClkinForward(self.platform)
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data_pads = [platform.request("sfp", i) for i in range(4)]
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self.submodules.gt_drtio = gtx_7series.GTX(
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@ -257,8 +268,25 @@ class GenericMaster(SoCCore):
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self.comb += ext_async_rst.eq(self.sys_crg.clk_sw_fsm.o_clk_sw & ~gtx0.tx_init.done)
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self.specials += MultiReg(self.sys_crg.clk_sw_fsm.o_clk_sw & self.sys_crg.mmcm_locked, self.gt_drtio.clk_path_ready, odomain="bootstrap")
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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if with_wrpll:
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clk_synth = platform.request("cdr_clk_clean_fabric")
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clk_synth_se = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
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self.submodules.wrpll_refclk = wrpll.SMAFrequencyMultiplier(platform.request("sma_clkin"))
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self.submodules.wrpll = wrpll.WRPLL(
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platform=self.platform,
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cd_ref=self.wrpll_refclk.cd_ref,
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main_clk_se=clk_synth_se)
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self.csr_devices.append("wrpll_refclk")
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self.csr_devices.append("wrpll")
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self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
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self.config["HAS_SI549"] = None
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self.config["WRPLL_REF_CLK"] = "SMA_CLKIN"
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else:
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self.submodules += SMAClkinForward(self.platform)
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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@ -400,6 +428,7 @@ class GenericMaster(SoCCore):
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class GenericSatellite(SoCCore):
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def __init__(self, description, acpki=False):
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clk_freq = description["rtio_frequency"]
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with_wrpll = description["enable_wrpll"]
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self.acpki = acpki
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@ -551,14 +580,30 @@ class GenericSatellite(SoCCore):
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self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk"),
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rx_synchronizer=self.rx_synchronizer,
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ultrascale=False,
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rtio_clk_freq=self.gt_drtio.rtio_clk_freq)
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self.csr_devices.append("siphaser")
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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if with_wrpll:
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clk_synth = platform.request("cdr_clk_clean_fabric")
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clk_synth_se = Signal()
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platform.add_period_constraint(clk_synth.p, 8.0)
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self.specials += Instance("IBUFGDS", p_DIFF_TERM="TRUE", p_IBUF_LOW_PWR="FALSE", i_I=clk_synth.p, i_IB=clk_synth.n, o_O=clk_synth_se)
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self.submodules.wrpll = wrpll.WRPLL(
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platform=self.platform,
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cd_ref=self.gt_drtio.cd_rtio_rx0,
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main_clk_se=clk_synth_se)
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self.submodules.wrpll_skewtester = wrpll.SkewTester(self.rx_synchronizer)
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self.csr_devices.append("wrpll_skewtester")
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self.csr_devices.append("wrpll")
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self.comb += self.ps7.core.core0.nfiq.eq(self.wrpll.ev.irq)
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self.config["HAS_SI549"] = None
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self.config["WRPLL_REF_CLK"] = "GT_CDR"
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else:
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk"),
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rx_synchronizer=self.rx_synchronizer,
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ultrascale=False,
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rtio_clk_freq=self.gt_drtio.rtio_clk_freq)
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self.csr_devices.append("siphaser")
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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gtx0 = self.gt_drtio.gtxs[0]
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platform.add_false_path_constraints(
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