forked from M-Labs/artiq-zynq
kasli soc: add rtio_frequency cfg for runtime
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c261897658
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@ -135,6 +135,7 @@ class GenericStandalone(SoCCore):
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]
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fix_serdes_timing_path(platform)
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self.submodules.bootstrap = GTPBootstrapClock(self.platform, clk_freq)
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self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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self.submodules.sys_crg = zynq_clocking.SYSCRG(self.platform, self.ps7, clk_synth_se_buf)
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@ -242,6 +243,7 @@ class GenericMaster(SoCCore):
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pads=data_pads,
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clk_freq=clk_freq)
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self.csr_devices.append("gt_drtio")
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self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
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self.config["CLOCK_FREQUENCY"] = int(clk_freq)
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txout_buf = Signal()
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