forked from M-Labs/artiq-zynq
change write_rustc_cfg_file to follow artiq repo
This commit is contained in:
MorganTL
parent
1516327c26
commit
0e6309b95e
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@ -85,9 +85,6 @@ class GTP125BootstrapClock(Module):
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class GenericStandalone(SoCCore):
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def __init__(self, description, acpki=False):
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self.acpki = acpki
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self.rustc_cfg = dict()
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self.rustc_cfg["hw_rev"] = description["hw_rev"]
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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@ -98,10 +95,12 @@ class GenericStandalone(SoCCore):
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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self.config["HW_REV"] = description["hw_rev"]
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self.submodules += SMAClkinForward(self.platform)
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["si5324_soft_reset"] = None
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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clk_synth = platform.request("cdr_clk_clean_fabric")
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clk_synth_se = Signal()
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@ -140,14 +139,14 @@ class GenericStandalone(SoCCore):
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self.csr_devices.append("rtio_core")
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.config["KI_IMPL"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.config["KI_IMPL"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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@ -167,7 +166,7 @@ class GenericStandalone(SoCCore):
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self.csr_devices.append("rtio_analyzer")
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if has_grabber:
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self.rustc_cfg["has_grabber"] = None
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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for grabber in self.grabber_csr_group:
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self.platform.add_false_path_constraints(
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@ -179,9 +178,6 @@ class GenericMaster(SoCCore):
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clk_freq = description["rtio_frequency"]
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self.acpki = acpki
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self.rustc_cfg = dict()
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self.rustc_cfg["hw_rev"] = description["hw_rev"]
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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@ -192,6 +188,8 @@ class GenericMaster(SoCCore):
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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self.config["HW_REV"] = description["hw_rev"]
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self.submodules += SMAClkinForward(self.platform)
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data_pads = [platform.request("sfp", i) for i in range(4)]
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@ -219,8 +217,8 @@ class GenericMaster(SoCCore):
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self.bootstrap.cd_bootstrap.clk, self.sys_crg.cd_sys.clk)
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fix_serdes_timing_path(platform)
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["si5324_soft_reset"] = None
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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self.rtio_channels = []
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has_grabber = any(peripheral["type"] == "grabber" for peripheral in description["peripherals"])
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@ -265,8 +263,8 @@ class GenericMaster(SoCCore):
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memory_address = self.axi2csr.register_port(coreaux.get_tx_port(), size)
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self.axi2csr.register_port(coreaux.get_rx_port(), size)
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, size * 2)
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self.rustc_cfg["has_drtio"] = None
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self.rustc_cfg["has_drtio_routing"] = None
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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@ -275,14 +273,14 @@ class GenericMaster(SoCCore):
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self.csr_devices.append("rtio_core")
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.config["KI_IMPL"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.config["KI_IMPL"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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@ -306,7 +304,7 @@ class GenericMaster(SoCCore):
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self.csr_devices.append("rtio_analyzer")
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if has_grabber:
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self.rustc_cfg["has_grabber"] = None
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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@ -323,9 +321,6 @@ class GenericSatellite(SoCCore):
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clk_freq = description["rtio_frequency"]
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self.acpki = acpki
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self.rustc_cfg = dict()
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self.rustc_cfg["hw_rev"] = description["hw_rev"]
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platform = kasli_soc.Platform()
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platform.toolchain.bitstream_commands.extend([
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@ -336,6 +331,8 @@ class GenericSatellite(SoCCore):
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ident = "acpki_" + ident
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SoCCore.__init__(self, platform=platform, csr_data_width=32, ident=ident, ps_cd_sys=False)
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self.config["HW_REV"] = description["hw_rev"]
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data_pads = [platform.request("sfp", i) for i in range(4)]
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self.submodules.gt_drtio = gtx_7series.GTX(
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@ -420,21 +417,21 @@ class GenericSatellite(SoCCore):
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# and registered in PS interface
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# manually, because software refers to rx/tx by halves of entire memory block, not names
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self.add_memory_region(memory_name, self.mem_map["csr"] + memory_address, mem_size * 2)
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self.rustc_cfg["has_drtio"] = None
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self.rustc_cfg["has_drtio_routing"] = None
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.add_csr_group("drtiorep", drtiorep_csr_group)
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if self.acpki:
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self.rustc_cfg["ki_impl"] = "acp"
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self.config["KI_IMPL"] = "acp"
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self.submodules.rtio = acpki.KernelInitiator(self.rtio_tsc,
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bus=self.ps7.s_axi_acp,
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user=self.ps7.s_axi_acp_user,
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evento=self.ps7.event.o)
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self.csr_devices.append("rtio")
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else:
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self.rustc_cfg["ki_impl"] = "csr"
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self.config["KI_IMPL"] = "csr"
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self.submodules.rtio = rtio.KernelInitiator(self.rtio_tsc, now64=True)
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self.csr_devices.append("rtio")
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@ -461,7 +458,7 @@ class GenericSatellite(SoCCore):
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self.csr_devices.append("rtio_analyzer")
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rtio_clk_period = 1e9/clk_freq
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self.rustc_cfg["rtio_frequency"] = str(clk_freq/1e6)
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self.config["RTIO_FREQUENCY"] = str(clk_freq/1e6)
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("cdr_clk"),
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@ -469,16 +466,15 @@ class GenericSatellite(SoCCore):
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ultrascale=False,
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rtio_clk_freq=self.gt_drtio.rtio_clk_freq)
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self.csr_devices.append("siphaser")
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self.rustc_cfg["has_si5324"] = None
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self.rustc_cfg["has_siphaser"] = None
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self.rustc_cfg["si5324_soft_reset"] = None
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self.config["HAS_SI5324"] = None
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self.config["SI5324_SOFT_RESET"] = None
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gtx0 = self.gt_drtio.gtxs[0]
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platform.add_false_path_constraints(
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gtx0.txoutclk, gtx0.rxoutclk)
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if has_grabber:
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self.rustc_cfg["has_grabber"] = None
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self.config["HAS_GRABBER"] = None
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self.add_csr_group("grabber", self.grabber_csr_group)
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# no RTIO CRG here
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@ -503,11 +499,14 @@ def write_csr_file(soc, filename):
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def write_rustc_cfg_file(soc, filename):
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with open(filename, "w") as f:
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for k, v in sorted(soc.rustc_cfg.items(), key=itemgetter(0)):
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if v is None:
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f.write("{}\n".format(k))
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for name, origin, busword, obj in soc.get_csr_regions():
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f.write("has_{}\n".format(name.lower()))
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for name, value in soc.get_constants():
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if name.upper().startswith("CONFIG_"):
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if value is None:
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f.write("{}\n".format(name.lower()[7:]))
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else:
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f.write("{}=\"{}\"\n".format(k, v))
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f.write("{}=\"{}\"\n".format(name.lower()[7:], str(value)))
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def main():
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