forked from renet/ENC424J600
Fix poor & unimplemented code
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6b47c05843
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ae0d77cbf1
@ -129,7 +129,7 @@ impl <'c, SPI: Transfer<u8>,
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rx_packet.update_frame_length();
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// Read frame bytes
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let mut frame_buf = [0; rx::RAW_FRAME_LENGTH_MAX];
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self.spi_port.read_rxdat(&mut frame_buf, rx_packet.get_frame_length() as u32)?;
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self.spi_port.read_rxdat(&mut frame_buf, rx_packet.get_frame_length())?;
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rx_packet.copy_frame_from(&frame_buf[1..]);
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// Set ERXTAIL pointer to (next_addr - 2)
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if self.rx_buf.get_next_addr() > rx::ERXST_DEFAULT {
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@ -152,7 +152,7 @@ impl <'c, SPI: Transfer<u8>,
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// 1-byte Opcode is included
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let mut txdat_buf: [u8; tx::RAW_FRAME_LENGTH_MAX + 1] = [0; tx::RAW_FRAME_LENGTH_MAX + 1];
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packet.write_frame_to(&mut txdat_buf[1..]);
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self.spi_port.write_txdat(&mut txdat_buf, packet.get_frame_length() as u32)?;
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self.spi_port.write_txdat(&mut txdat_buf, packet.get_frame_length())?;
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// Set ETXST to packet start address
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self.spi_port.write_reg_16b(spi::addrs::ETXST, self.tx_buf.get_next_addr())?;
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// Set ETXLEN to packet length
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28
src/spi.rs
28
src/spi.rs
@ -1,10 +1,7 @@
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use core::fmt;
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use embedded_hal::{
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blocking::spi::Transfer,
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digital::v2::OutputPin,
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spi,
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};
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use crate::rx;
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pub mod interfaces {
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use embedded_hal::spi;
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@ -64,6 +61,7 @@ pub enum SpiPortError {
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TransferError
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}
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#[allow(unused_must_use)]
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impl <SPI: Transfer<u8>,
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NSS: OutputPin> SpiPort<SPI, NSS> {
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// TODO: return as Result()
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@ -78,19 +76,19 @@ impl <SPI: Transfer<u8>,
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pub fn read_reg_8b(&mut self, addr: u8) -> Result<u8, SpiPortError> {
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// Using RCRU instruction to read using unbanked (full) address
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let mut r_data = self.rw_addr_u8(opcodes::RCRU, addr, 0)?;
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let r_data = self.rw_addr_u8(opcodes::RCRU, addr, 0)?;
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Ok(r_data)
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}
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pub fn read_reg_16b(&mut self, lo_addr: u8) -> Result<u16, SpiPortError> {
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let mut r_data_lo = self.read_reg_8b(lo_addr)?;
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let mut r_data_hi = self.read_reg_8b(lo_addr + 1)?;
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let r_data_lo = self.read_reg_8b(lo_addr)?;
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let r_data_hi = self.read_reg_8b(lo_addr + 1)?;
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// Combine top and bottom 8-bit to return 16-bit
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Ok(((r_data_hi as u16) << 8) | r_data_lo as u16)
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}
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// Currently requires manual slicing (buf[1..]) for the data read back
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pub fn read_rxdat<'a>(&mut self, buf: &'a mut [u8], data_length: u32)
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pub fn read_rxdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
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-> Result<(), SpiPortError> {
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let r_valid = self.r_n(buf, opcodes::RERXDATA, data_length)?;
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Ok(r_valid)
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@ -98,7 +96,7 @@ impl <SPI: Transfer<u8>,
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// Currenly requires actual data to be stored in buf[1..] instead of buf[0..]
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// TODO: Maybe better naming?
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pub fn write_txdat<'a>(&mut self, buf: &'a mut [u8], data_length: u32)
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pub fn write_txdat<'a>(&mut self, buf: &'a mut [u8], data_length: usize)
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-> Result<(), SpiPortError> {
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let w_valid = self.w_n(buf, opcodes::WEGPDATA, data_length)?;
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Ok(w_valid)
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@ -137,7 +135,7 @@ impl <SPI: Transfer<u8>,
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Ok(buf[2])
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},
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// TODO: Maybe too naive?
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Err(e) => {
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Err(_) => {
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// Disable chip select
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self.nss.set_high();
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Err(SpiPortError::TransferError)
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@ -150,20 +148,20 @@ impl <SPI: Transfer<u8>,
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// Returns a reference to the data returned
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// Note: buf must be at least (data_length + 1)-byte long
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// TODO: Check and raise error for array size < (data_length + 1)
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fn r_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: u32)
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fn r_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
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-> Result<(), SpiPortError> {
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// Enable chip select
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self.nss.set_low();
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// Start writing to SLAVE
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buf[0] = opcode;
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match self.spi.transfer(buf) {
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match self.spi.transfer(&mut buf[..data_length+1]) {
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Ok(_) => {
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// Disable chip select
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self.nss.set_high();
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Ok(())
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},
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// TODO: Maybe too naive?
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Err(e) => {
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Err(_) => {
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// Disable chip select
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self.nss.set_high();
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Err(SpiPortError::TransferError)
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@ -173,21 +171,21 @@ impl <SPI: Transfer<u8>,
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// Note: buf[0] is currently reserved for opcode to overwrite
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// TODO: Actual data should start from buf[0], not buf[1]
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fn w_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: u32)
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fn w_n<'a>(&mut self, buf: &'a mut [u8], opcode: u8, data_length: usize)
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-> Result<(), SpiPortError> {
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// Enable chip select
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self.nss.set_low();
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// Start writing to SLAVE
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buf[0] = opcode;
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// TODO: Maybe need to copy data to buf later on
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match self.spi.transfer(buf) {
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match self.spi.transfer(&mut buf[..data_length+1]) {
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Ok(_) => {
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// Disable chip select
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self.nss.set_high();
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Ok(())
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},
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// TODO: Maybe too naive?
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Err(e) => {
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Err(_) => {
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// Disable chip select
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self.nss.set_high();
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Err(SpiPortError::TransferError)
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