forked from renet/ENC424J600
Add reading SFR registers via SPI
* uses stm32f4xx_hal crate
This commit is contained in:
parent
5479912ab0
commit
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293
Cargo.lock
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293
Cargo.lock
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28
Cargo.toml
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28
Cargo.toml
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[package]
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categories = ["embedded", "no-std"]
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name = "enc424j600"
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description = "Embbeded Rust Ethernet driver for ENC424J600 Ethernet controller with SPI interface, compatible with STM32F4xx"
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authors = ["Harry Ho <hh@m-labs.hk>"]
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version = "0.1.0"
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keywords = ["ethernet", "eth", "enc424j600", "stm32", "stm32f4xx"]
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repository = "https://github.com/smoltcp-rs/ENC424J600"
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edition = "2018"
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[dependencies]
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volatile-register = "0.2"
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aligned = "0.3"
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stm32f4xx-hal = { version = "0.8" , optional = true }
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smoltcp = { version = "0.6.0", default-features = false, features = ["proto-ipv4", "proto-ipv6", "socket-icmp", "socket-udp", "socket-tcp", "log", "verbose", "ethernet"], optional = true }
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log = { version = "0.4", optional = true }
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[features]
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smoltcp-phy = ["smoltcp", "log"]
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stm32f407 = ["stm32f4xx-hal/stm32f407"]
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default = []
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[profile.release]
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codegen-units = 1
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incremental = false
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debug = true
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opt-level = "s"
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lto = true
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4
src/lib.rs
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4
src/lib.rs
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#![no_std]
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/// STM32F4xx-HAL specific implementations
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pub mod spi;
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84
src/spi.rs
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84
src/spi.rs
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use core::fmt;
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use stm32f4xx_hal::{
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hal::{
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blocking::spi::Transfer,
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digital::v2::OutputPin,
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},
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time::MegaHertz,
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spi,
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};
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/// Must use SPI mode cpol=0, cpha=0
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pub const SPI_MODE: spi::Mode = spi::Mode {
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polarity: spi::Polarity::IdleLow,
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phase: spi::Phase::CaptureOnFirstTransition,
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};
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/// Max freq = 14 MHz
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pub const SPI_CLOCK: MegaHertz = MegaHertz(14);
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/// SPI Opcodes
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const RCRU: u8 = 0b00100000;
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const WCRU: u8 = 0b00100010;
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/// Struct for SPI I/O interface on ENC424J600
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/// Note: stm32f4xx_hal::spi's pins include: SCK, MISO, MOSI
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pub struct SpiPort<SPI: Transfer<u8>,
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NSS: OutputPin> {
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spi: SPI,
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nss: NSS,
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}
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impl <SPI: Transfer<u8, Error = E>,
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NSS: OutputPin,
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E: fmt::Debug> SpiPort<SPI, NSS> {
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// TODO: return as Result()
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pub fn new(spi: SPI, mut nss: NSS) -> Self {
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nss.set_high();
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SpiPort {
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spi,
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nss
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}
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}
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pub fn read_reg_8b(&mut self, addr: u8) -> Result<u8, SPI::Error> {
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// Using RCRU instruction to read using unbanked (full) address
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let mut r_data = self.transfer(RCRU, addr, 0)?;
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Ok(r_data)
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}
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pub fn read_reg_16b(&mut self, lo_addr: u8) -> Result<u16, SPI::Error> {
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let mut r_data_lo = self.read_reg_8b(lo_addr)?;
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let mut r_data_hi = self.read_reg_8b(lo_addr + 1)?;
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// Combine top and bottom 8-bit to return 16-bit
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Ok(((r_data_hi as u16) << 8) | r_data_lo as u16)
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}
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pub fn write_reg_8b(&mut self, addr: u8, data: u8) -> Result<u8, SPI::Error> {
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// TODO: addr should be separated from w_data
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// Using WCRU instruction to write using unbanked (full) address
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self.transfer(WCRU, addr, data)?;
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Ok(0x01) // TODO: should not be just 0x01
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}
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fn transfer(&mut self, opcode: u8, addr: u8, data: u8)
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-> Result<u8, SPI::Error> {
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// TODO: Currently assumes read/write data is only 1-byte
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// Enable chip select
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self.nss.set_low();
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// Start writing to SLAVE
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// TODO: don't just use 3 bytes
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let mut buf: [u8; 3] = [0; 3];
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buf[0] = opcode;
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buf[1] = addr;
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buf[2] = data;
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let result = self.spi.transfer(&mut buf);
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// Disable chip select
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self.nss.set_high();
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match result {
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Ok(_) => Ok(buf[2]),
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Err(e) => Err(e),
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}
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}
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}
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