forked from M-Labs/zynq-rs
81 lines
1.8 KiB
Rust
81 lines
1.8 KiB
Rust
pub trait ReadableRegister<T> {
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fn get(&self) -> T;
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}
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macro_rules! def_reg_get {
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($name:ty, $type:ty, $asm_instr:tt) => {
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impl ReadableRegister<$type> for $name {
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#[inline(always)]
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fn get(&self) -> $type {
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let mut value;
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unsafe { asm!($asm_instr : "=r" (value) ::: "volatile") }
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value
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}
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}
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}
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}
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pub trait WritableRegister<T> {
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fn set(&self, value: T);
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}
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macro_rules! def_reg_set {
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($name:ty, $type:ty, $asm_instr:tt) => {
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impl WritableRegister<$type> for $name {
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#[inline(always)]
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fn set(&self, value: $type) {
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unsafe { asm!($asm_instr :: "r" (value) :: "volatile") }
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}
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}
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}
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}
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/// Stack Pointer
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pub struct SP;
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def_reg_get!(SP, u32, "mov $0, sp");
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def_reg_set!(SP, u32, "mov sp, $0");
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/// Link register (function call return address)
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pub struct LR;
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def_reg_get!(LR, u32, "mov $0, lr");
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def_reg_set!(LR, u32, "mov lr, $0");
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pub struct MPIDR;
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def_reg_get!(MPIDR, u32, "mrc p15, 0, $0, c0, c0, 5");
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/// Invalidate TLBs
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pub fn tlbiall() {
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unsafe {
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asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
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}
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}
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/// Invalidate I-Cache
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pub fn iciallu() {
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unsafe {
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asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
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}
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}
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/// Invalidate Branch Predictor Array
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pub fn bpiall() {
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unsafe {
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asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
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}
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}
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/// Invalidate D-Cache
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pub fn dccisw() {
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// TODO: $0 is r11 at what value?
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unsafe {
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asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
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}
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}
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/// Enable I-Cache and D-Cache
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pub fn sctlr() {
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unsafe {
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asm!("mcr p15, 0, $0, c1, c0, 0" :: "r" (0x1004) :: "volatile");
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}
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}
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