forked from M-Labs/zynq-rs
54 lines
1.6 KiB
Rust
54 lines
1.6 KiB
Rust
use core::mem::uninitialized;
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use crate::{register, register_bit, register_bits, register_bits_typed, regs::*};
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/// Descriptor entry
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struct DescEntry {
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word0: DescWord0,
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word1: DescWord1,
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}
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register!(desc_word0, DescWord0, RW, u32);
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register_bits!(desc_word0, address, u32, 0, 31);
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register!(desc_word1, DescWord1, RW, u32);
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register_bits!(desc_word1, length, u16, 0, 13);
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register_bit!(desc_word1, last_buffer, 15);
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register_bit!(desc_word1, no_crc_append, 16);
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register_bits!(desc_word1, csum_offload_errors, u8, 20, 22);
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register_bit!(desc_word1, late_collision_tx_error, 26);
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register_bit!(desc_word1, ahb_frame_corruption, 27);
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register_bit!(desc_word1, retry_limit_exceeded, 29);
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/// marks last descriptor in list
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register_bit!(desc_word1, wrap, 30);
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/// true if owned by software, false if owned by hardware
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register_bit!(desc_word1, used, 31);
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/// Number of descriptors
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pub const DESCS: usize = 8;
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#[repr(C)]
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pub struct DescList<'a> {
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list: [DescEntry; DESCS],
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buffers: [&'a [u8]; DESCS],
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}
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impl<'a> DescList<'a> {
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pub fn new(buffers: [&'a [u8]; DESCS]) -> Self {
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let mut list: [DescEntry; DESCS] = unsafe { uninitialized() };
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for i in 0..DESCS {
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let buffer_addr = &buffers[i][0] as *const _ as u32;
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list[i].word0.write(
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DescWord0::zeroed()
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.address(buffer_addr)
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);
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list[i].word1.write(
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DescWord1::zeroed()
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.used(true)
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.wrap(i == DESCS - 1)
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);
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}
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DescList { list, buffers }
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}
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}
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