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f50018092c
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mmu: add early memory barrier to L1Table.update()
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2020-06-18 01:27:34 +02:00 |
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6761575b30
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mmu: add L1Table.update()
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2020-06-18 01:27:34 +02:00 |
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aebce435e2
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mmu: switch bufferable=1 (writeback) for DDR pages
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2020-06-18 01:27:34 +02:00 |
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66cd0c7630
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libcortex_a9: allow access for full 1GB of DDR
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2020-05-09 02:35:39 +02:00 |
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0d4d021b1b
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clean up
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2020-05-01 01:17:53 +02:00 |
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008a995429
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libcortex_a9: remove mmu::l1_table alignment through linker script
no longer needed, #[repr(16384)] works now
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2020-04-30 03:38:27 +02:00 |
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282b4dc69a
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link.x: reduce alignment, use all remaining OCM for .stack
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2020-04-28 02:50:07 +02:00 |
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965a00801e
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libcortex_a9: set DDR pages non-bufferable to fix eth dma
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2020-03-31 01:09:28 +02:00 |
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cf1983e543
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split into lib{register, cortex_a9, board_zynq, board_zc706} crates
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2019-12-17 23:35:58 +01:00 |
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