forked from M-Labs/zynq-rs
eth: model rx/tx state with type parameters
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74bd81f87f
commit
f07a541c99
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@ -3,15 +3,16 @@ use crate::slcr;
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pub mod phy;
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pub mod phy;
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mod regs;
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mod regs;
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mod rx;
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pub mod rx;
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mod tx;
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pub mod tx;
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pub struct Eth<'rx> {
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pub struct Eth<RX, TX> {
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regs: &'static mut regs::RegisterBlock,
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regs: &'static mut regs::RegisterBlock,
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rx: Option<rx::DescList<'rx>>,
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rx: RX,
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tx: TX,
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}
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}
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impl<'rx> Eth<'rx> {
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impl Eth<(), ()> {
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pub fn default(macaddr: [u8; 6]) -> Self {
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pub fn default(macaddr: [u8; 6]) -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr::RegisterBlock::unlocked(|slcr| {
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// MDIO
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// MDIO
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@ -140,20 +141,42 @@ impl<'rx> Eth<'rx> {
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});
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});
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let regs = regs::RegisterBlock::gem0();
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let regs = regs::RegisterBlock::gem0();
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let rx = None;
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Self::from_regs(regs, macaddr)
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let mut eth = Eth { regs, rx }.init();
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eth.configure(macaddr);
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eth
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}
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}
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pub fn gem1(macaddr: [u8; 6]) -> Self {
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pub fn gem1(macaddr: [u8; 6]) -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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// Enable gem1 ref clock
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slcr.gem1_rclk_ctrl.write(
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slcr::RclkCtrl::zeroed()
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.clkact(true)
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);
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// 0x0050_0801: 8, 5: 100 Mb/s
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slcr.gem1_clk_ctrl.write(
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slcr::ClkCtrl::zeroed()
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.clkact(true)
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.srcsel(slcr::PllSource::IoPll)
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.divisor(8)
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.divisor1(5)
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);
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});
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let regs = regs::RegisterBlock::gem1();
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let regs = regs::RegisterBlock::gem1();
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let rx = None;
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Self::from_regs(regs, macaddr)
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let mut eth = Eth { regs, rx }.init();
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}
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fn from_regs(regs: &'static mut regs::RegisterBlock, macaddr: [u8; 6]) -> Self {
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let mut eth = Eth {
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regs,
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rx: (),
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tx: (),
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}.init();
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eth.configure(macaddr);
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eth.configure(macaddr);
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eth
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eth
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}
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}
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}
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impl<RX, TX> Eth<RX, TX> {
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fn init(mut self) -> Self {
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fn init(mut self) -> Self {
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// Clear the Network Control register.
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// Clear the Network Control register.
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self.regs.net_ctrl.write(regs::NetCtrl::zeroed());
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self.regs.net_ctrl.write(regs::NetCtrl::zeroed());
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@ -274,14 +297,19 @@ impl<'rx> Eth<'rx> {
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);
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);
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}
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}
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pub fn start_rx(&mut self, rx_buffers: [&'rx mut [u8]; rx::DESCS]) {
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pub fn start_rx<'rx>(self, rx_buffers: [&'rx mut [u8]; rx::DESCS]) -> Eth<rx::DescList<'rx>, TX> {
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self.rx = Some(rx::DescList::new(rx_buffers));
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let new_self = Eth {
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let list_addr = self.rx.as_ref().unwrap() as *const _ as u32;
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regs: self.regs,
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rx: rx::DescList::new(rx_buffers),
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tx: self.tx,
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};
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let list_addr = &new_self.rx as *const _ as u32;
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assert!(list_addr & 0b11 == 0);
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assert!(list_addr & 0b11 == 0);
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self.regs.rx_qbar.write(
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new_self.regs.rx_qbar.write(
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regs::RxQbar::zeroed()
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regs::RxQbar::zeroed()
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.rx_q_baseaddr(list_addr >> 2)
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.rx_q_baseaddr(list_addr >> 2)
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);
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);
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new_self
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}
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}
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fn wait_phy_idle(&self) {
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fn wait_phy_idle(&self) {
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@ -289,7 +317,7 @@ impl<'rx> Eth<'rx> {
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}
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}
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}
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}
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impl<'rx> phy::PhyAccess for Eth<'rx> {
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impl<RX, TX> phy::PhyAccess for Eth<RX, TX> {
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fn read_phy(&mut self, addr: u8, reg: u8) -> u16 {
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fn read_phy(&mut self, addr: u8, reg: u8) -> u16 {
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self.wait_phy_idle();
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self.wait_phy_idle();
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self.regs.phy_maint.write(
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self.regs.phy_maint.write(
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10
src/main.rs
10
src/main.rs
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@ -6,6 +6,7 @@
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#![feature(compiler_builtins_lib)]
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#![feature(compiler_builtins_lib)]
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use core::fmt::Write;
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use core::fmt::Write;
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use core::mem::uninitialized;
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use r0::zero_bss;
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use r0::zero_bss;
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use compiler_builtins as _;
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use compiler_builtins as _;
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@ -92,6 +93,15 @@ fn main() {
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}
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}
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while !uart.tx_fifo_empty() {}
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while !uart.tx_fifo_empty() {}
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let mut rx_buffers = [[0u8; 1536]; eth::rx::DESCS];
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let mut rx_buffer_ptrs: [&mut [u8]; eth::rx::DESCS] = unsafe {
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uninitialized()
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};
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for (i, (ptr, buf)) in rx_buffer_ptrs.iter_mut().zip(rx_buffers.iter_mut()).enumerate() {
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*ptr = buf;
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}
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let mut eth = eth.start_rx(rx_buffer_ptrs);
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loop {}
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loop {}
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panic!("End");
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panic!("End");
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}
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}
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