forked from M-Labs/zynq-rs
uart: make baudrate configurable, run at 115,200 baud
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15883293ac
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ea62d4fdec
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@ -50,10 +50,11 @@ unsafe fn boot_core0() -> ! {
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}
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fn main() {
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let mut uart = Uart::uart1();
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writeln!(uart, "Hello World\r").unwrap();
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for i in 0.. {
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writeln!(uart, "i={}\r", i).unwrap();
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let mut uart = Uart::uart1(115_200);
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loop {
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for i in 0.. {
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writeln!(uart, "i={}\r", i);
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}
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}
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let eth = eth::Eth::gem0();
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@ -8,12 +8,16 @@ use crate::regs::*;
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mod regs;
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mod baud_rate_gen;
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/// Determined through experimentation. Actually supposed to be
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/// 1 GHz (IO PLL) / 0x14 (slcr.UART_CLK_CTRL[DIVISOR]) = 50 MHz.
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const UART_REF_CLK: u32 = 45_000_000;
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pub struct Uart {
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regs: &'static mut regs::RegisterBlock,
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}
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impl Uart {
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pub fn uart1() -> Self {
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pub fn uart1(baudrate: u32) -> Self {
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super::slcr::with_slcr(|| {
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let uart_rst_ctrl = super::slcr::UartRstCtrl::new();
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uart_rst_ctrl.reset_uart1();
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@ -36,7 +40,7 @@ impl Uart {
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let self_ = Uart {
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regs: regs::RegisterBlock::uart1(),
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};
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self_.configure();
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self_.configure(baudrate);
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self_
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}
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@ -49,7 +53,7 @@ impl Uart {
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);
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}
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pub fn configure(&self) {
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pub fn configure(&self, baudrate: u32) {
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// Configure UART character frame
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// * Disable clock-divider
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// * 8-bit
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@ -67,7 +71,7 @@ impl Uart {
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self.disable_rx();
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self.disable_tx();
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baud_rate_gen::configure(&self.regs, 50_000_000, 9_600);
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baud_rate_gen::configure(&self.regs, UART_REF_CLK, baudrate);
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// Enable controller
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self.reset_rx();
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