forked from M-Labs/zynq-rs
parent
66c3470afd
commit
b7690c9702
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@ -10,9 +10,9 @@ mod baud_rate_gen;
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/// Determined through experimentation. Actually supposed to be
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/// Determined through experimentation. Actually supposed to be
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/// 1 GHz (IO PLL) / 0x14 (slcr.UART_CLK_CTRL[DIVISOR]) = 50 MHz.
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/// 1 GHz (IO PLL) / 0x14 (slcr.UART_CLK_CTRL[DIVISOR]) = 50 MHz.
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#[cfg(feature = "target_zc706")]
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#[cfg(feature = "target_zc706")]
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const UART_REF_CLK: u32 = 45_000_000;
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const UART_REF_CLK: u32 = 50_000_000;
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_cora_z7_10")]
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const UART_REF_CLK: u32 = 66_000_000;
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const UART_REF_CLK: u32 = 72_000_000;
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pub struct Uart {
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pub struct Uart {
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regs: &'static mut regs::RegisterBlock,
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regs: &'static mut regs::RegisterBlock,
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