forked from M-Labs/zynq-rs
uart: add baud_rate_gen
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@ -0,0 +1,43 @@
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use crate::regs::*;
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use super::regs::{RegisterBlock, BaudRateGen, BaudRateDiv};
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const BDIV_MIN: u8 = 4;
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const BDIV_MAX: u8 = 255;
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const CD_MAX: u16 = 65535;
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/// Algorithm as in the Linux 5.1 driver
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pub fn configure(regs: &RegisterBlock, mut clk: u32, baud: u32) {
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if regs.mode.read().clks() {
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clk /= 8;
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}
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let mut best = None;
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for bdiv in BDIV_MIN..=BDIV_MAX {
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let bdiv: u32 = bdiv.into();
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let cd = clk / (baud * (bdiv + 1));
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if cd < 1 || cd > CD_MAX.into() {
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continue;
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}
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let actual_baud = clk / (cd * (bdiv + 1));
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let error = if baud > actual_baud {
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baud - actual_baud
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} else {
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actual_baud - baud
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};
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let better = best
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.map(|(_cd, _bdiv, best_error)| error < best_error)
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.unwrap_or(true);
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if better {
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best = Some((cd as u16, bdiv as u8, error));
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}
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}
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match best {
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Some((cd, bdiv, error)) => {
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regs.baud_rate_gen.write(BaudRateGen::zeroed().cd(cd));
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regs.baud_rate_divider.write(BaudRateDiv::zeroed().bdiv(bdiv));
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}
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None => panic!("Cannot configure baud rate")
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}
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}
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@ -6,6 +6,7 @@ use volatile_register::RW;
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use crate::regs::*;
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use crate::regs::*;
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mod regs;
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mod regs;
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mod baud_rate_gen;
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pub struct Uart {
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pub struct Uart {
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regs: &'static mut regs::RegisterBlock,
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regs: &'static mut regs::RegisterBlock,
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@ -49,12 +50,12 @@ impl Uart {
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}
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}
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pub fn configure(&self) {
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pub fn configure(&self) {
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// Confiugre UART character frame
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// Configure UART character frame
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// * Disable clock-divider
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// * Disable clock-divider
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// * 8-bit
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// * 8-bit
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// * 1 stop bit
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// * 1 stop bit
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// * Normal channel mode
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// * Normal channel mode
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// * no parity
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// * No parity
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let parity_mode = regs::ParityMode::None;
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let parity_mode = regs::ParityMode::None;
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self.regs.mode.write(
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self.regs.mode.write(
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regs::Mode::zeroed()
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regs::Mode::zeroed()
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@ -66,12 +67,7 @@ impl Uart {
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self.disable_rx();
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self.disable_rx();
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self.disable_tx();
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self.disable_tx();
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// 9,600 baud
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baud_rate_gen::configure(&self.regs, 50_000_000, 9_600);
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self.regs.baud_rate_gen.write(regs::BaudRateGen::zeroed().cd(651));
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self.regs.baud_rate_divider.write(regs::BaudRateDiv::zeroed().bdiv(7));
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// // 115,200 baud
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// self.regs.baud_rate_gen.write(regs::BaudRateGen::zeroed().cd(62));
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// self.regs.baud_rate_divider.write(regs::BaudRateDiv::zeroed().bdiv(6));
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// Enable controller
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// Enable controller
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self.reset_rx();
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self.reset_rx();
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