forked from M-Labs/zynq-rs
zynq::clocks: unlock slcr in enable_io()
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261455877d
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afd96bd887
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@ -90,6 +90,30 @@ impl CpuClocks {
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pll / u32::from(uart_clk_ctrl.divisor())
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}
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// 25.10.4 PLLs
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pub fn enable_io(target_clock: u32) {
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let fdiv = (target_clock / PS_CLK).min(66) as u16;
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.io_pll_ctrl.modify(|_, w| w
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.pll_pwrdwn(false)
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.pll_bypass_force(true)
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.pll_fdiv(fdiv)
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);
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slcr.io_pll_ctrl.modify(|_, w| w
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.pll_reset(true)
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);
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slcr.io_pll_ctrl.modify(|_, w| w
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.pll_reset(false)
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);
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while ! slcr.pll_status.read().io_pll_lock() {}
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slcr.io_pll_ctrl.modify(|_, w| w
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.pll_bypass_force(false)
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.pll_bypass_qual(false)
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);
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});
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}
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// 25.10.4 PLLs
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pub fn enable_ddr(target_clock: u32) {
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