forked from M-Labs/zynq-rs
EBAZ4205 Initial commit
This commit is contained in:
parent
b2b3e5c933
commit
a75568bd42
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@ -8,6 +8,7 @@ edition = "2018"
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[features]
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[features]
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target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
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target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
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target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7"]
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target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7"]
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target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205"]
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target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"]
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target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"]
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target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc"]
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target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc"]
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default = ["target_zc706"]
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default = ["target_zc706"]
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@ -116,6 +116,7 @@ pub fn main_core0() {
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#[cfg(any(
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#[cfg(any(
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feature = "target_zc706",
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feature = "target_zc706",
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feature = "target_ebaz4205",
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feature = "target_redpitaya",
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feature = "target_redpitaya",
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feature = "target_kasli_soc",
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feature = "target_kasli_soc",
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))]
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))]
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@ -203,7 +204,7 @@ pub fn main_core0() {
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let mut err_cdwn = timer.countdown();
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let mut err_cdwn = timer.countdown();
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let mut err_state = true;
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let mut err_state = true;
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let mut led = zynq::error_led::ErrorLED::error_led();
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let mut led = zynq::error_led::ErrorLED::error_led();
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task::spawn( async move {
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task::spawn( async move {
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loop {
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loop {
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led.toggle(err_state);
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led.toggle(err_state);
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err_state = !err_state;
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err_state = !err_state;
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@ -8,6 +8,7 @@ edition = "2018"
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[features]
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[features]
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target_zc706 = []
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target_zc706 = []
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target_coraz7 = []
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target_coraz7 = []
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target_ebaz4205 = []
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target_redpitaya = []
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target_redpitaya = []
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target_kasli_soc = []
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target_kasli_soc = []
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ipv6 = [ "smoltcp/proto-ipv6" ]
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ipv6 = [ "smoltcp/proto-ipv6" ]
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@ -6,6 +6,8 @@ use super::slcr;
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pub const PS_CLK: u32 = 33_333_333;
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pub const PS_CLK: u32 = 33_333_333;
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#[cfg(feature = "target_coraz7")]
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#[cfg(feature = "target_coraz7")]
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pub const PS_CLK: u32 = 50_000_000;
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pub const PS_CLK: u32 = 50_000_000;
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#[cfg(feature = "target_ebaz4205")]
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pub const PS_CLK: u32 = 33_333_333;
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#[cfg(feature = "target_redpitaya")]
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#[cfg(feature = "target_redpitaya")]
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pub const PS_CLK: u32 = 33_333_333;
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pub const PS_CLK: u32 = 33_333_333;
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#[cfg(feature = "target_kasli_soc")]
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#[cfg(feature = "target_kasli_soc")]
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@ -16,6 +16,10 @@ const DDR_FREQ: u32 = 666_666_666;
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/// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz
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/// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz
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const DDR_FREQ: u32 = 525_000_000;
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const DDR_FREQ: u32 = 525_000_000;
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#[cfg(feature = "target_ebaz4205")]
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/// EtronTech Memory EM6GD16EWKG-12H: 800 MHz DDR3 at 533 MHz
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const DDR_FREQ: u32 = 533_333_333;
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#[cfg(feature = "target_redpitaya")]
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#[cfg(feature = "target_redpitaya")]
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/// Alliance Memory AS4C256M16D3B: 800 MHz DDR3 at 533 MHz
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/// Alliance Memory AS4C256M16D3B: 800 MHz DDR3 at 533 MHz
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const DDR_FREQ: u32 = 533_333_333;
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const DDR_FREQ: u32 = 533_333_333;
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@ -147,22 +151,23 @@ impl DdrRam {
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.output_en(slcr::DdriobOutputEn::Obuf);
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_zc706")]
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#[cfg(feature = "target_zc706")]
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let data1_config = data0_config.clone();
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let data1_config = data0_config.clone();
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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#[cfg(any(
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feature = "target_coraz7",
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feature = "target_ebaz4205",
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feature = "target_redpitaya",
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feature = "target_kasli_soc",
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))]
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let data0_config = slcr::DdriobConfig::zeroed()
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let data0_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::VrefDifferential)
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.inp_type(slcr::DdriobInputType::VrefDifferential)
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.term_en(true)
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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#[cfg(any(
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let data1_config = slcr::DdriobConfig::zeroed()
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feature = "target_coraz7",
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.pullup_en(true);
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feature = "target_ebaz4205",
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#[cfg(feature = "target_redpitaya")]
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feature = "target_redpitaya",
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let data0_config = slcr::DdriobConfig::zeroed()
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feature = "target_kasli_soc",
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.inp_type(slcr::DdriobInputType::VrefDifferential)
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))]
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_redpitaya")]
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let data1_config = slcr::DdriobConfig::zeroed()
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let data1_config = slcr::DdriobConfig::zeroed()
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.pullup_en(true);
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.pullup_en(true);
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slcr.ddriob_data0.write(data0_config);
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slcr.ddriob_data0.write(data0_config);
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@ -176,22 +181,23 @@ impl DdrRam {
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.output_en(slcr::DdriobOutputEn::Obuf);
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_zc706")]
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#[cfg(feature = "target_zc706")]
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let diff1_config = diff0_config.clone();
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let diff1_config = diff0_config.clone();
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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#[cfg(any(
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feature = "target_coraz7",
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feature = "target_ebaz4205",
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feature = "target_redpitaya",
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feature = "target_kasli_soc",
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))]
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let diff0_config = slcr::DdriobConfig::zeroed()
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let diff0_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::Differential)
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.inp_type(slcr::DdriobInputType::Differential)
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.term_en(true)
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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#[cfg(any(
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let diff1_config = slcr::DdriobConfig::zeroed()
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feature = "target_coraz7",
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.pullup_en(true);
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feature = "target_ebaz4205",
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#[cfg(feature = "target_redpitaya")]
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feature = "target_redpitaya",
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let diff0_config = slcr::DdriobConfig::zeroed()
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feature = "target_kasli_soc",
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.inp_type(slcr::DdriobInputType::Differential)
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))]
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_redpitaya")]
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let diff1_config = slcr::DdriobConfig::zeroed()
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let diff1_config = slcr::DdriobConfig::zeroed()
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.pullup_en(true);
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.pullup_en(true);
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slcr.ddriob_diff0.write(diff0_config);
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slcr.ddriob_diff0.write(diff0_config);
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@ -210,7 +216,12 @@ impl DdrRam {
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slcr.ddriob_drive_slew_clock.write(0x00F9861C);
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slcr.ddriob_drive_slew_clock.write(0x00F9861C);
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}
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}
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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#[cfg(any(
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feature = "target_coraz7",
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feature = "target_ebaz4205",
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feature = "target_redpitaya",
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feature = "target_kasli_soc",
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))]
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slcr.ddriob_ddr_ctrl.modify(|_, w| w
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slcr.ddriob_ddr_ctrl.modify(|_, w| w
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.vref_int_en(false)
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.vref_int_en(false)
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.vref_ext_en_lower(true)
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.vref_ext_en_lower(true)
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@ -224,13 +235,6 @@ impl DdrRam {
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.vref_ext_en_lower(false)
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.vref_ext_en_lower(false)
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.vref_ext_en_upper(false)
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.vref_ext_en_upper(false)
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);
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);
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#[cfg(feature = "target_redpitaya")]
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slcr.ddriob_ddr_ctrl.modify(|_, w| w
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.vref_int_en(false)
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.vref_ext_en_lower(true)
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.vref_ext_en_upper(false)
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.refio_en(true)
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);
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});
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});
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}
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}
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@ -242,6 +246,13 @@ impl DdrRam {
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.t_rfc_min(0x9e)
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.t_rfc_min(0x9e)
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.post_selfref_gap_x32(0x10)
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.post_selfref_gap_x32(0x10)
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);
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);
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#[cfg(feature = "target_ebaz4205")]
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self.regs.dram_param0.write(
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regs::DramParam0::zeroed()
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.t_rc(0x1a) // 48.75 ns / 1.875 ns = 26 clock cycles
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.t_rfc_min(0x56) // 160 ns / 1.875 ns = 85.333 --> 86 clock cycles
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.post_selfref_gap_x32(0x10) // Default value
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);
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#[cfg(feature = "target_redpitaya")]
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#[cfg(feature = "target_redpitaya")]
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self.regs.dram_param0.write(
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self.regs.dram_param0.write(
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regs::DramParam0::zeroed()
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regs::DramParam0::zeroed()
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@ -256,6 +267,12 @@ impl DdrRam {
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.t_rfc_min(0x56)
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.t_rfc_min(0x56)
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.post_selfref_gap_x32(0x10)
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.post_selfref_gap_x32(0x10)
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);
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);
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#[cfg(feature = "target_ebaz4205")]
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self.regs.dram_param1.modify(
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|_, w| w
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.t_faw(0x16) // 40 ns / 1.875 ns = 21.33 --> 22 clock cycles
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.t_ras_min(0x13) // 35 ns / 1.875 ns = 18.66 --> 19 clock cycles
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);
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#[cfg(feature = "target_redpitaya")]
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#[cfg(feature = "target_redpitaya")]
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self.regs.dram_param1.modify(
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self.regs.dram_param1.modify(
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|_, w| w
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|_, w| w
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@ -277,6 +294,11 @@ impl DdrRam {
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.rd2pre(0x4)
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.rd2pre(0x4)
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.t_rcd(0x7)
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.t_rcd(0x7)
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);
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);
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#[cfg(feature = "target_ebaz4205")]
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self.regs.dram_param3.modify(
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|_, w| w
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.t_rp(7)
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);
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#[cfg(feature = "target_redpitaya")]
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#[cfg(feature = "target_redpitaya")]
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self.regs.dram_param3.modify(
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self.regs.dram_param3.modify(
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|_, w| w
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|_, w| w
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@ -298,19 +320,21 @@ impl DdrRam {
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.emr(0x4)
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.emr(0x4)
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);
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);
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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#[cfg(any(
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feature = "target_coraz7",
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feature = "target_ebaz4205",
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feature = "target_redpitaya",
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feature = "target_kasli_soc",
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))]
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self.regs.phy_configs[2].modify(
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self.regs.phy_configs[2].modify(
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|_, w| w.data_slice_in_use(false)
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|_, w| w.data_slice_in_use(false)
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);
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);
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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#[cfg(any(
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self.regs.phy_configs[3].modify(
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feature = "target_coraz7",
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|_, w| w.data_slice_in_use(false)
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feature = "target_ebaz4205",
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);
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feature = "target_redpitaya",
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#[cfg(feature = "target_redpitaya")]
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feature = "target_kasli_soc",
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self.regs.phy_configs[2].modify(
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))]
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|_, w| w.data_slice_in_use(false)
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);
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#[cfg(feature = "target_redpitaya")]
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self.regs.phy_configs[3].modify(
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self.regs.phy_configs[3].modify(
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|_, w| w.data_slice_in_use(false)
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|_, w| w.data_slice_in_use(false)
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);
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);
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@ -354,7 +378,11 @@ impl DdrRam {
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.gatelvl_init_ratio(0xee)
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.gatelvl_init_ratio(0xee)
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);
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);
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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#[cfg(any(
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feature = "target_coraz7",
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feature = "target_ebaz4205",
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feature = "target_kasli_soc"),
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)]
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self.regs.reg_64.modify(
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self.regs.reg_64.modify(
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|_, w| w
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|_, w| w
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.phy_ctrl_slave_ratio(0x100)
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.phy_ctrl_slave_ratio(0x100)
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@ -390,9 +418,12 @@ impl DdrRam {
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fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) {
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fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) {
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#[cfg(feature = "target_zc706")]
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#[cfg(feature = "target_zc706")]
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let width = regs::DataBusWidth::Width32bit;
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let width = regs::DataBusWidth::Width32bit;
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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#[cfg(any(
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let width = regs::DataBusWidth::Width16bit;
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feature = "target_coraz7",
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#[cfg(feature = "target_redpitaya")]
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feature = "target_ebaz4205",
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feature = "target_redpitaya",
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feature = "target_kasli_soc",
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))]
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let width = regs::DataBusWidth::Width16bit;
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let width = regs::DataBusWidth::Width16bit;
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self.regs.ddrc_ctrl.modify(|_, w| w
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self.regs.ddrc_ctrl.modify(|_, w| w
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.soft_rstb(false)
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.soft_rstb(false)
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@ -410,6 +441,7 @@ impl DdrRam {
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}
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}
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#[cfg(any(
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#[cfg(any(
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feature = "target_coraz7",
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feature = "target_coraz7",
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feature = "target_ebaz4205",
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feature = "target_redpitaya",
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feature = "target_redpitaya",
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feature = "target_kasli_soc",
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feature = "target_kasli_soc",
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))]
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))]
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@ -446,6 +478,7 @@ impl DdrRam {
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let megabytes = 1023;
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let megabytes = 1023;
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#[cfg(any(
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#[cfg(any(
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feature = "target_coraz7",
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feature = "target_coraz7",
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feature = "target_ebaz4205",
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feature = "target_redpitaya",
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feature = "target_redpitaya",
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feature = "target_kasli_soc",
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feature = "target_kasli_soc",
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))]
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))]
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@ -83,6 +83,7 @@ pub struct Phy {
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const OUI_MARVELL: u32 = 0x005043;
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const OUI_MARVELL: u32 = 0x005043;
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const OUI_REALTEK: u32 = 0x000732;
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const OUI_REALTEK: u32 = 0x000732;
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const OUI_LANTIQ : u32 = 0x355969;
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const OUI_LANTIQ : u32 = 0x355969;
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const OUI_ICPLUS : u32 = 0x02430c;
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|
||||||
//only change pages on Kasli-SoC's Marvel 88E11xx
|
//only change pages on Kasli-SoC's Marvel 88E11xx
|
||||||
#[cfg(feature="target_kasli_soc")]
|
#[cfg(feature="target_kasli_soc")]
|
||||||
|
@ -117,6 +118,13 @@ impl Phy {
|
||||||
model: 0,
|
model: 0,
|
||||||
..
|
..
|
||||||
}) => true,
|
}) => true,
|
||||||
|
Some(PhyIdentifier {
|
||||||
|
oui: OUI_ICPLUS,
|
||||||
|
// IP101G-DS-R01
|
||||||
|
model: 5,
|
||||||
|
rev: 4,
|
||||||
|
..
|
||||||
|
}) => true,
|
||||||
_ => false,
|
_ => false,
|
||||||
}
|
}
|
||||||
}).map(|addr| Phy { addr })
|
}).map(|addr| Phy { addr })
|
||||||
|
@ -141,7 +149,7 @@ impl Phy {
|
||||||
{
|
{
|
||||||
#[cfg(feature="target_kasli_soc")]
|
#[cfg(feature="target_kasli_soc")]
|
||||||
pa.write_phy(self.addr, PAGE_REGISTER, PR::page().into());
|
pa.write_phy(self.addr, PAGE_REGISTER, PR::page().into());
|
||||||
|
|
||||||
let reg = pa.read_phy(self.addr, PR::addr()).into();
|
let reg = pa.read_phy(self.addr, PR::addr()).into();
|
||||||
let reg = f(reg);
|
let reg = f(reg);
|
||||||
pa.write_phy(self.addr, PR::addr(), reg.into())
|
pa.write_phy(self.addr, PR::addr(), reg.into())
|
||||||
|
@ -160,7 +168,7 @@ impl Phy {
|
||||||
PA: PhyAccess,
|
PA: PhyAccess,
|
||||||
F: FnMut(Leds) -> Leds,
|
F: FnMut(Leds) -> Leds,
|
||||||
{
|
{
|
||||||
self.modify_reg(pa, f)
|
self.modify_reg(pa, f)
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn get_control<PA: PhyAccess>(&self, pa: &mut PA) -> Control {
|
pub fn get_control<PA: PhyAccess>(&self, pa: &mut PA) -> Control {
|
||||||
|
|
|
@ -116,8 +116,8 @@ impl Sdio {
|
||||||
.speed(true),
|
.speed(true),
|
||||||
);
|
);
|
||||||
}
|
}
|
||||||
// redpitaya card detect pin
|
// kasli_soc and redpitaya card detect pin
|
||||||
#[cfg(any(feature = "target_redpitaya", feature = "target_kasli_soc"))]
|
#[cfg(any(feature = "target_kasli_soc", feature = "target_redpitaya"))]
|
||||||
{
|
{
|
||||||
unsafe {
|
unsafe {
|
||||||
slcr.sd0_wp_cd_sel.write(46 << 16);
|
slcr.sd0_wp_cd_sel.write(46 << 16);
|
||||||
|
@ -128,6 +128,20 @@ impl Sdio {
|
||||||
.speed(true),
|
.speed(true),
|
||||||
);
|
);
|
||||||
}
|
}
|
||||||
|
// ebaz4205 card detect pin
|
||||||
|
#[cfg(feature = "target_ebaz4205")]
|
||||||
|
{
|
||||||
|
unsafe {
|
||||||
|
slcr.sd0_wp_cd_sel.write(34 << 16);
|
||||||
|
}
|
||||||
|
slcr.mio_pin_34.write(
|
||||||
|
slcr::MioPin34::zeroed()
|
||||||
|
.io_type(slcr::IoBufferType::Lvcmos33)
|
||||||
|
.pullup(true)
|
||||||
|
.speed(true),
|
||||||
|
);
|
||||||
|
}
|
||||||
|
|
||||||
slcr.sdio_rst_ctrl.reset_sdio0();
|
slcr.sdio_rst_ctrl.reset_sdio0();
|
||||||
slcr.aper_clk_ctrl.enable_sdio0();
|
slcr.aper_clk_ctrl.enable_sdio0();
|
||||||
slcr.sdio_clk_ctrl.enable_sdio0();
|
slcr.sdio_clk_ctrl.enable_sdio0();
|
||||||
|
|
|
@ -47,7 +47,11 @@ impl DerefMut for LazyUart {
|
||||||
LazyUart::Uninitialized => {
|
LazyUart::Uninitialized => {
|
||||||
#[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
|
#[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
|
||||||
let uart = Uart::uart0(UART_RATE);
|
let uart = Uart::uart0(UART_RATE);
|
||||||
#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
|
#[cfg(any(
|
||||||
|
feature = "target_zc706",
|
||||||
|
feature = "target_ebaz4205",
|
||||||
|
feature = "target_kasli_soc",
|
||||||
|
))]
|
||||||
let uart = Uart::uart1(UART_RATE);
|
let uart = Uart::uart1(UART_RATE);
|
||||||
*self = LazyUart::Initialized(uart);
|
*self = LazyUart::Initialized(uart);
|
||||||
self
|
self
|
||||||
|
|
|
@ -79,6 +79,39 @@ impl Uart {
|
||||||
self_
|
self_
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#[cfg(feature = "target_ebaz4205")]
|
||||||
|
pub fn uart1(baudrate: u32) -> Self {
|
||||||
|
slcr::RegisterBlock::unlocked(|slcr| {
|
||||||
|
// Route UART 1 RxD/TxD Signals to MIO Pins
|
||||||
|
// TX pin
|
||||||
|
slcr.mio_pin_24.write(
|
||||||
|
slcr::MioPin24::zeroed()
|
||||||
|
.l3_sel(0b111)
|
||||||
|
.io_type(slcr::IoBufferType::Lvcmos33)
|
||||||
|
.pullup(true)
|
||||||
|
);
|
||||||
|
// RX pin
|
||||||
|
slcr.mio_pin_25.write(
|
||||||
|
slcr::MioPin25::zeroed()
|
||||||
|
.tri_enable(true)
|
||||||
|
.l3_sel(0b111)
|
||||||
|
.io_type(slcr::IoBufferType::Lvcmos33)
|
||||||
|
.pullup(true)
|
||||||
|
);
|
||||||
|
});
|
||||||
|
|
||||||
|
slcr::RegisterBlock::unlocked(|slcr| {
|
||||||
|
slcr.uart_rst_ctrl.reset_uart1();
|
||||||
|
slcr.aper_clk_ctrl.enable_uart1();
|
||||||
|
slcr.uart_clk_ctrl.enable_uart1();
|
||||||
|
});
|
||||||
|
let mut self_ = Uart {
|
||||||
|
regs: regs::RegisterBlock::uart1(),
|
||||||
|
};
|
||||||
|
self_.configure(baudrate);
|
||||||
|
self_
|
||||||
|
}
|
||||||
|
|
||||||
pub fn write_byte(&mut self, value: u8) {
|
pub fn write_byte(&mut self, value: u8) {
|
||||||
while self.tx_fifo_full() {}
|
while self.tx_fifo_full() {}
|
||||||
|
|
||||||
|
|
|
@ -13,6 +13,7 @@ log = "0.4"
|
||||||
[features]
|
[features]
|
||||||
target_zc706 = []
|
target_zc706 = []
|
||||||
target_coraz7 = []
|
target_coraz7 = []
|
||||||
|
target_ebaz4205 = []
|
||||||
target_redpitaya = []
|
target_redpitaya = []
|
||||||
target_kasli_soc = []
|
target_kasli_soc = []
|
||||||
ipv6 = []
|
ipv6 = []
|
||||||
|
|
|
@ -55,6 +55,10 @@ pub fn get_addresses(cfg: &Config) -> NetAddresses {
|
||||||
let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x55]);
|
let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x55]);
|
||||||
#[cfg(feature = "target_redpitaya")]
|
#[cfg(feature = "target_redpitaya")]
|
||||||
let mut ipv4_addr = IpAddress::v4(192, 168, 1, 55);
|
let mut ipv4_addr = IpAddress::v4(192, 168, 1, 55);
|
||||||
|
#[cfg(feature = "target_ebaz4205")]
|
||||||
|
let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x56]);
|
||||||
|
#[cfg(feature = "target_ebaz4205")]
|
||||||
|
let mut ipv4_addr = IpAddress::v4(192, 168, 1, 56);
|
||||||
#[cfg(feature = "target_kasli_soc")]
|
#[cfg(feature = "target_kasli_soc")]
|
||||||
let mut hardware_addr = get_address_from_eeprom();
|
let mut hardware_addr = get_address_from_eeprom();
|
||||||
#[cfg(feature = "target_kasli_soc")]
|
#[cfg(feature = "target_kasli_soc")]
|
||||||
|
|
|
@ -8,6 +8,7 @@ edition = "2018"
|
||||||
[features]
|
[features]
|
||||||
target_zc706 = ["libboard_zynq/target_zc706"]
|
target_zc706 = ["libboard_zynq/target_zc706"]
|
||||||
target_coraz7 = ["libboard_zynq/target_coraz7"]
|
target_coraz7 = ["libboard_zynq/target_coraz7"]
|
||||||
|
target_ebaz4205 = ["libboard_zynq/target_ebaz4205"]
|
||||||
target_redpitaya = ["libboard_zynq/target_redpitaya"]
|
target_redpitaya = ["libboard_zynq/target_redpitaya"]
|
||||||
target_kasli_soc = ["libboard_zynq/target_kasli_soc"]
|
target_kasli_soc = ["libboard_zynq/target_kasli_soc"]
|
||||||
panic_handler = []
|
panic_handler = []
|
||||||
|
|
|
@ -0,0 +1,33 @@
|
||||||
|
# The contents of this file are partially dependend on
|
||||||
|
# the adapter that you have. Please modify accordingly.
|
||||||
|
adapter driver ftdi
|
||||||
|
ftdi vid_pid 0x0403 0x6010
|
||||||
|
ftdi channel 0
|
||||||
|
# Every pin set as high impedance except TCK, TDI, TDO and TMS
|
||||||
|
ftdi layout_init 0x0008 0x000b
|
||||||
|
|
||||||
|
# nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip)
|
||||||
|
# This choice is arbitrary. Use other GPIO pin if desired.
|
||||||
|
ftdi layout_signal nSRST -data 0x0020 -oe 0x0020
|
||||||
|
|
||||||
|
transport select jtag
|
||||||
|
adapter speed 10000
|
||||||
|
|
||||||
|
set PL_TAPID 0x13722093
|
||||||
|
set SMP 1
|
||||||
|
|
||||||
|
source ./zynq-7000.cfg
|
||||||
|
|
||||||
|
reset_config srst_only srst_open_drain
|
||||||
|
adapter srst pulse_width 250
|
||||||
|
adapter srst delay 400
|
||||||
|
|
||||||
|
source ./common.cfg
|
||||||
|
|
||||||
|
reset halt
|
||||||
|
|
||||||
|
# Disable MMU
|
||||||
|
targets $_TARGETNAME_1
|
||||||
|
arm mcr 15 0 1 0 0 [expr { [arm mrc 15 0 1 0 0] & ~0xd }]
|
||||||
|
targets $_TARGETNAME_0
|
||||||
|
arm mcr 15 0 1 0 0 [expr { [arm mrc 15 0 1 0 0] & ~0xd }]
|
|
@ -8,6 +8,7 @@ edition = "2018"
|
||||||
[features]
|
[features]
|
||||||
target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
|
target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
|
||||||
target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7", "libconfig/target_coraz7"]
|
target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7", "libconfig/target_coraz7"]
|
||||||
|
target_ebaz4205 = ["libboard_zynq/target_ebaz4205", "libsupport_zynq/target_ebaz4205", "libconfig/target_ebaz4205"]
|
||||||
target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"]
|
target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"]
|
||||||
target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc"]
|
target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc"]
|
||||||
default = ["target_zc706"]
|
default = ["target_zc706"]
|
||||||
|
|
Loading…
Reference in New Issue