forked from M-Labs/zynq-rs
experiments: enabled L2 cache
...and removed some trailing spaces
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@ -27,6 +27,7 @@ use libboard_zynq::{
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};
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};
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use libcortex_a9::{
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use libcortex_a9::{
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mutex::Mutex,
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mutex::Mutex,
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l2c::enable_l2_cache,
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sync_channel::{Sender, Receiver},
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sync_channel::{Sender, Receiver},
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sync_channel,
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sync_channel,
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regs::{MPIDR, SP},
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regs::{MPIDR, SP},
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@ -86,6 +87,7 @@ pub fn restart_core1() {
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#[no_mangle]
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#[no_mangle]
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pub fn main_core0() {
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pub fn main_core0() {
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// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
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// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
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enable_l2_cache();
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println!("\nzc706 main");
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println!("\nzc706 main");
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let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
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let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
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interrupt_controller.enable_interrupts();
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interrupt_controller.enable_interrupts();
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