forked from M-Labs/zynq-rs
dmac: remove unused module
This commit is contained in:
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84f1380f48
commit
855d94c48e
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@ -1,3 +0,0 @@
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//! PrimeCell DMA Controller (PL330)
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mod regs;
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@ -1,386 +0,0 @@
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use libregister::{
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register, register_at,
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register_bit, register_bits, register_bits_typed,
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};
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#[allow(unused)]
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#[repr(C)]
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pub struct RegisterBlock {
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pub ds: Ds,
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pub dpc: DPc,
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pub inten: Inten,
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pub es: Es,
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pub intstatus: IntStatus,
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pub intclr: IntClr,
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pub fsm: Fsm,
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pub fsc: Fsc,
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pub ftm: Ftm,
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pub ftc: [Ftc; 8],
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pub cs0: Cs,
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pub cpc0: Cpc,
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pub cs1: Cs,
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pub cpc1: Cpc,
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pub cs2: Cs,
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pub cpc2: Cpc,
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pub cs3: Cs,
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pub cpc3: Cpc,
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pub cs4: Cs,
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pub cpc4: Cpc,
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pub cs5: Cs,
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pub cpc5: Cpc,
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pub cs6: Cs,
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pub cpc6: Cpc,
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pub cs7: Cs,
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pub cpc7: Cpc,
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pub sa0: Sa,
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pub da0: Da,
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pub cc0: Cc,
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pub lc0_0: Lc,
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pub lc0_1: Lc,
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pub sa1: Sa,
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pub da1: Da,
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pub cc1: Cc,
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pub lc1_0: Lc,
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pub lc1_1: Lc,
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pub sa2: Sa,
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pub da2: Da,
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pub cc2: Cc,
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pub lc2_0: Lc,
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pub lc2_1: Lc,
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pub sa3: Sa,
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pub da3: Da,
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pub cc3: Cc,
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pub lc3_0: Lc,
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pub lc3_1: Lc,
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pub sa4: Sa,
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pub da4: Da,
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pub cc4: Cc,
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pub lc4_0: Lc,
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pub lc4_1: Lc,
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pub sa5: Sa,
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pub da5: Da,
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pub cc5: Cc,
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pub lc5_0: Lc,
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pub lc5_1: Lc,
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pub sa6: Sa,
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pub da6: Da,
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pub cc6: Cc,
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pub lc6_0: Lc,
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pub lc6_1: Lc,
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pub sa7: Sa,
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pub da7: Da,
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pub cc7: Cc,
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pub lc7_0: Lc,
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pub lc7_1: Lc,
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pub dbgstatus: DbgStatus,
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pub dbgcmd: DbgCmd,
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pub dbginst0: DbgInst0,
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pub dbginst1: DbgInst1,
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pub cr0: Cr0,
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pub cr1: Cr1,
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pub cr2: Cr2,
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pub cr3: Cr3,
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pub cr4: Cr4,
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pub crdn: Crdn,
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pub wd: Wd,
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pub periph_id_0: PeriphId0,
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pub periph_id_1: PeriphId1,
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pub periph_id_2: PeriphId2,
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pub periph_id_3: PeriphId3,
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pub pcell_id_0: PCellId0,
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pub pcell_id_1: PCellId1,
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pub pcell_id_2: PCellId2,
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pub pcell_id_3: PCellId3,
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}
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register_at!(RegisterBlock, 0xF8004000, dmac0_ns);
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register_at!(RegisterBlock, 0xF8003000, dmac0_s);
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impl RegisterBlock {
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pub fn channel_regs(&mut self, channel: usize) -> Option<ChannelRegisters>
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{
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match channel {
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0 => Some(ChannelRegisters {
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ftc: &mut self.ftc[0],
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cs: &mut self.cs0,
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cpc: &mut self.cpc0,
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sa: &mut self.sa0,
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da: &mut self.da0,
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cc: &mut self.cc0,
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lc: [&mut self.lc0_0, &mut self.lc0_1],
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}),
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1 => Some(ChannelRegisters {
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ftc: &mut self.ftc[1],
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cs: &mut self.cs1,
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cpc: &mut self.cpc1,
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sa: &mut self.sa1,
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da: &mut self.da1,
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cc: &mut self.cc1,
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lc: [&mut self.lc1_0, &mut self.lc1_1],
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}),
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2 => Some(ChannelRegisters {
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ftc: &mut self.ftc[2],
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cs: &mut self.cs2,
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cpc: &mut self.cpc2,
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sa: &mut self.sa2,
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da: &mut self.da2,
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cc: &mut self.cc2,
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lc: [&mut self.lc2_0, &mut self.lc2_1],
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}),
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3 => Some(ChannelRegisters {
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ftc: &mut self.ftc[3],
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cs: &mut self.cs3,
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cpc: &mut self.cpc3,
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sa: &mut self.sa3,
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da: &mut self.da3,
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cc: &mut self.cc3,
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lc: [&mut self.lc3_0, &mut self.lc3_1],
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}),
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4 => Some(ChannelRegisters {
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ftc: &mut self.ftc[4],
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cs: &mut self.cs4,
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cpc: &mut self.cpc4,
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sa: &mut self.sa4,
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da: &mut self.da4,
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cc: &mut self.cc4,
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lc: [&mut self.lc4_0, &mut self.lc4_1],
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}),
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5 => Some(ChannelRegisters {
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ftc: &mut self.ftc[5],
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cs: &mut self.cs5,
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cpc: &mut self.cpc5,
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sa: &mut self.sa5,
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da: &mut self.da5,
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cc: &mut self.cc5,
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lc: [&mut self.lc5_0, &mut self.lc5_1],
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}),
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6 => Some(ChannelRegisters {
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ftc: &mut self.ftc[6],
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cs: &mut self.cs6,
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cpc: &mut self.cpc6,
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sa: &mut self.sa6,
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da: &mut self.da6,
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cc: &mut self.cc6,
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lc: [&mut self.lc6_0, &mut self.lc6_1],
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}),
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7 => Some(ChannelRegisters {
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ftc: &mut self.ftc[7],
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cs: &mut self.cs7,
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cpc: &mut self.cpc7,
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sa: &mut self.sa7,
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da: &mut self.da7,
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cc: &mut self.cc7,
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lc: [&mut self.lc7_0, &mut self.lc7_1],
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}),
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_ => None,
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}
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}
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}
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pub struct ChannelRegisters<'a> {
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ftc: &'a mut Ftc,
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cs: &'a mut Cs,
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cpc: &'a mut Cpc,
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sa: &'a mut Sa,
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da: &'a mut Da,
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cc: &'a mut Cc,
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lc: [&'a mut Lc; 2],
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}
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#[allow(unused)]
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#[repr(u8)]
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pub enum WakeUpEvent{
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// @missing: there's a binary prefix ahead of this as per TRM 1173 Wakeup_event
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Event0 = 0b0000,
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Event1 = 0b0001,
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Event2 = 0b0010,
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Event3 = 0b0011,
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Event4 = 0b0100,
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Event5 = 0b0101,
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Event6 = 0b0110,
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Event7 = 0b0111,
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Event8 = 0b1000,
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Event9 = 0b1001,
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Event10 = 0b1010,
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Event11 = 0b1011,
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Event12 = 0b1100,
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Event13 = 0b1101,
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Event14 = 0b1110,
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Event15 = 0b1111,
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}
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#[allow(unused)]
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#[repr(u8)]
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pub enum DMAStatus{
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Stopped = 0b0000,
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Executing = 0b0001,
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CacheMiss = 0b0010,
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UpdatingPc = 0b0011,
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WaitingForEvent = 0b0100,
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Reserved0 = 0b0101,
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Reserved1 = 0b0110,
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Reserved2 = 0b0111,
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Reserved3 = 0b1000,
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Reserved4 = 0b1001,
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Reserved5 = 0b1010,
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Reserved6 = 0b1011,
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Reserved7 = 0b1100,
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Reserved8 = 0b1101,
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Reserved9 = 0b1110,
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Faulting = 0b1111,
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}
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register!(ds, Ds, RW, u32);
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register_bit!(ds, dns, 9);
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register_bits_typed!(ds, wakeup_event, u8, WakeUpEvent, 4, 8);
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register_bits_typed!(ds, dma_status, u8, DMAStatus, 0, 3);
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register!(dpc, DPc, RW, u32);
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register_bits!(dpc, pc_mgr, u8, 0, 31);
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register!(inten, Inten, RW, u32);
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register_bits!(inten, event_irq_select, u8, 0, 31);
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register!(es, Es, RW, u32);
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register_bits!(es, dmasev_active, u8, 0, 31);
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register!(intstatus, IntStatus, RW, u32);
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register_bits!(intstatus, irq_status, u8, 0, 31);
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register!(intclr, IntClr, RW, u32);
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register_bits!(intstatus, irq_clr, u8, 0, 31);
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register!(fsm, Fsm, RW, u32);
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register_bit!(fsm, fs_mgr, 0);
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register!(fsc, Fsc, RW, u32);
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register_bits!(fsc, fault_status, u8, 0, 7);
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register!(ftm, Ftm, RW, u32);
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register_bit!(ftm, dbg_instr, 30);
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register_bit!(ftm, instr_fetch_err, 16);
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register_bit!(ftm, mgr_evnt_err, 5);
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register_bit!(ftm, dmago_err, 4);
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register_bit!(ftm, operand_invalid, 1);
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register_bit!(ftm, undef_instr, 0);
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register!(ftc, Ftc, RW, u32);
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register_bit!(ftc, lockup_err, 31);
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register_bit!(ftc, dbg_instr, 30);
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register_bit!(ftc, data_read_err, 18);
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register_bit!(ftc, data_write_err, 17);
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register_bit!(ftc, instr_fetch_err, 16);
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register_bit!(ftc, st_data_unavailable, 13);
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register_bit!(ftc, mfifo_err, 12);
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register_bit!(ftc, ch_rdwr_err, 7);
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register_bit!(ftc, ch_periph_err, 6);
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register_bit!(ftc, ch_evnt_err, 5);
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register_bit!(ftc, operand_invalid, 1);
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register_bit!(ftc, undef_instr, 0);
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register!(cs, Cs, RW, u32);
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register_bit!(cs, cns, 21);
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register_bit!(cs, dmawfp_periph, 15);
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register_bit!(cs, dmawfp_b_ns, 14);
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register_bits!(cs, wakeup_num, u8, 4, 8);
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register_bits!(cs, channel_status, u8, 0, 3);
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register!(cpc, Cpc, RW, u32);
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register_bits!(cpc, pc_chnl, u8, 0, 31);
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register!(sa, Sa, RW, u32);
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register_bits!(sa, src_addr, u8, 0, 31);
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register!(da, Da, RW, u32);
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register_bits!(da, dest_addr, u8, 0, 31);
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register!(cc, Cc, RW, u32);
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register_bits!(cc, endian_swap_size, u8, 28, 30);
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register_bits!(cc, dst_cache_ctrl, u8, 25, 27);
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register_bits!(cc, dst_prot_ctrl, u8, 22, 24);
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register_bits!(cc, dst_burst_len, u8, 18, 21);
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register_bits!(cc, dst_burst_size, u8, 15, 17);
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register_bit!(cc, dst_inc, 14);
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register_bits!(cc, src_cache_ctrl, u8, 11, 13);
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register_bits!(cc, src_prot_ctrl, u8, 8, 10);
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register_bits!(cc, src_burst_len, u8, 4, 7);
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register_bits!(cc, src_burst_size, u8, 1, 3);
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register_bit!(cc, src_inc, 0);
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register!(lc0, Lc, RW, u32);
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register_bits!(lc0, loop_counter_iteration, u8, 0, 7);
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register!(dbgstatus, DbgStatus, RW, u32);
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register_bit!(dbgstatus, dbgstatus, 0);
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register!(dbgcmd, DbgCmd, RW, u32);
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register_bits!(dbgcmd, dbgcmd, u8, 0, 1);
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register!(dbginst0, DbgInst0, RW, u32);
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register_bits!(dbginst0, instruction_byte1, u8, 24, 31);
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register_bits!(dbginst0, instruction_byte0, u8, 16, 23);
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register_bits!(dbginst0, channel_num, u8, 8, 10);
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register_bit!(dbginst0, debug_thread, 0);
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register!(dbginst1, DbgInst1, RW, u32);
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register_bits!(dbginst1, instruction_byte5, u8, 24, 31);
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register_bits!(dbginst1, instruction_byte4, u8, 16, 23);
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register_bits!(dbginst1, instruction_byte3, u8, 8, 10);
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register_bits!(dbginst1, instruction_byte2, u8, 0, 7);
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register!(cr0, Cr0, RW, u32);
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register_bits!(cr0, num_events, u8, 17, 21);
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register_bits!(cr0, num_periph_req, u8, 12, 16);
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register_bits!(cr0, num_chnls, u8, 4, 6);
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register_bit!(cr0, mgr_ns_at_rst, 2);
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register_bit!(cr0, boot_en, 1);
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register_bit!(cr0, periph_req, 0);
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register!(cr1, Cr1, RW, u32);
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register_bits!(cr1, num_icache_lines, u8, 4, 7);
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register_bits!(cr1, icache_len, u8, 0, 2);
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register!(cr2, Cr2, RW, u32);
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register_bits!(cr2, boot_addr, u8, 0, 31);
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register!(cr3, Cr3, RW, u32);
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register_bits!(cr3, ins, u8, 0, 31);
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register!(cr4, Cr4, RW, u32);
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register_bits!(cr4, ins, u8, 0, 31);
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register!(crdn, Crdn, RW, u32);
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register_bits!(crdn, data_buffer_dep, u8, 20, 29);
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register_bits!(crdn, rd_q_dep, u8, 16, 19);
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register_bits!(crdn, rd_cap, u8, 12, 14);
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register_bits!(crdn, wr_q_dep, u8, 8, 11);
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register_bits!(crdn, wr_cap, u8, 4, 6);
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register_bits!(crdn, data_width, u8, 0, 2);
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register!(wd, Wd, RW, u32);
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register_bit!(wd, wd_irq_only, 0);
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register!(periph_id_0, PeriphId0, RW, u32);
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register_bits!(periph_id_0, part_number_0, u8, 0, 7);
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register!(periph_id_1, PeriphId1, RW, u32);
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register_bits!(periph_id_1, designer_0, u8, 4, 7);
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register_bits!(periph_id_1, part_number_1, u8, 0, 3);
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register!(periph_id_2, PeriphId2, RW, u32);
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register_bits!(periph_id_2, revision, u8, 4, 7);
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register_bits!(periph_id_2, designer_1, u8, 0, 3);
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register!(periph_id_3, PeriphId3, RW, u32);
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register_bit!(periph_id_3, integration_cfg, 0);
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register!(pcell_id_0, PCellId0, RW, u32);
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register_bits!(pcell_id_0, pcell_id_0, u8, 0, 7);
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register!(pcell_id_1, PCellId1, RW, u32);
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register_bits!(pcell_id_1, pcell_id_1, u8, 0, 7);
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register!(pcell_id_2, PCellId2, RW, u32);
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register_bits!(pcell_id_2, pcell_id_2, u8, 0, 7);
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register!(pcell_id_3, PCellId3, RW, u32);
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register_bits!(pcell_id_3, pcell_id_3, u8, 0, 7);
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@ -16,7 +16,6 @@ pub mod axi_gp;
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pub mod ddr;
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pub mod mpcore;
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pub mod flash;
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pub mod dmac;
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pub mod time;
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pub mod timer;
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pub mod sdio;
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