forked from M-Labs/zynq-rs
libsupport_zynq/ram: use core0 allocator by default.
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5850401d72
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84041a3154
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@ -19,7 +19,7 @@ unsafe impl Sync for CortexA9Alloc {}
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unsafe impl GlobalAlloc for CortexA9Alloc {
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unsafe fn alloc(&self, layout: Layout) -> *mut u8 {
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if MPIDR.read().cpu_id() == 0 {
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if cfg!(not(feature = "alloc_core")) || MPIDR.read().cpu_id() == 0 {
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self.0.get().as_mut()
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} else {
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self.1.get().as_mut()
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@ -31,7 +31,7 @@ unsafe impl GlobalAlloc for CortexA9Alloc {
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}
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unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) {
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if MPIDR.read().cpu_id() == 0 {
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if cfg!(not(feature = "alloc_core")) || MPIDR.read().cpu_id() == 0 {
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self.0.get().as_mut()
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} else {
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self.1.get().as_mut()
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@ -83,7 +83,7 @@ pub fn init_alloc_core1() {
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fn alloc_error(layout: core::alloc::Layout) -> ! {
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let id = MPIDR.read().cpu_id();
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let heap = unsafe {
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if id == 0 {
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if cfg!(not(feature = "alloc_core")) || id == 0 {
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ALLOCATOR.0.get()
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} else {
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ALLOCATOR.1.get()
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