forked from M-Labs/zynq-rs
libsupport_zynq/abort: moved core1 restart code to user code.
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02a2c4d1e3
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7d38c53c18
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@ -16,5 +16,5 @@ embedded-hal = "0.2"
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libregister = { path = "../libregister" }
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libregister = { path = "../libregister" }
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libcortex_a9 = { path = "../libcortex_a9" }
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libcortex_a9 = { path = "../libcortex_a9" }
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libboard_zynq = { path = "../libboard_zynq" }
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libboard_zynq = { path = "../libboard_zynq" }
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libsupport_zynq = { path = "../libsupport_zynq" }
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libsupport_zynq = { path = "../libsupport_zynq", default-features = false, features = ["panic_handler"]}
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libasync = { path = "../libasync" }
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libasync = { path = "../libasync" }
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@ -1,6 +1,7 @@
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#![no_std]
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#![no_std]
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#![no_main]
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#![no_main]
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#![feature(const_in_array_repeat_expressions)]
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#![feature(const_in_array_repeat_expressions)]
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#![feature(naked_functions)]
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extern crate alloc;
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extern crate alloc;
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@ -14,7 +15,7 @@ use libboard_zynq::{
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self as zynq,
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self as zynq,
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clocks::source::{ArmPll, ClockSource, IoPll},
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clocks::source::{ArmPll, ClockSource, IoPll},
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clocks::Clocks,
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clocks::Clocks,
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print, println,
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print, println, stdio,
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mpcore,
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mpcore,
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gic,
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gic,
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smoltcp::{
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smoltcp::{
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@ -28,22 +29,65 @@ use libcortex_a9::{
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mutex::Mutex,
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mutex::Mutex,
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sync_channel::{Sender, Receiver},
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sync_channel::{Sender, Receiver},
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sync_channel,
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sync_channel,
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regs::{MPIDR, SP},
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asm
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};
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};
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use libregister::RegisterR;
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use libregister::{RegisterR, RegisterW};
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use libsupport_zynq::{
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use libsupport_zynq::{
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boot, ram,
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boot, ram,
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};
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};
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use log::{info, warn};
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use log::{info, warn};
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use core::sync::atomic::{AtomicBool, Ordering};
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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static mut CORE1_REQ: (Sender<usize>, Receiver<usize>) = sync_channel!(usize, 10);
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static mut CORE1_REQ: (Sender<usize>, Receiver<usize>) = sync_channel!(usize, 10);
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static mut CORE1_RES: (Sender<usize>, Receiver<usize>) = sync_channel!(usize, 10);
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static mut CORE1_RES: (Sender<usize>, Receiver<usize>) = sync_channel!(usize, 10);
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extern "C" {
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static mut __stack1_start: u32;
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}
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static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
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#[link_section = ".text.boot"]
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#[no_mangle]
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#[naked]
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pub unsafe extern "C" fn IRQ() {
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if MPIDR.read().cpu_id() == 1{
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let mpcore = mpcore::RegisterBlock::new();
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let mut gic = gic::InterruptController::new(mpcore);
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let id = gic.get_interrupt_id();
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if id.0 == 0 {
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gic.end_interrupt(id);
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asm::exit_irq();
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SP.write(&mut __stack1_start as *mut _ as u32);
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asm::enable_irq();
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CORE1_RESTART.store(false, Ordering::Relaxed);
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asm::sev();
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main_core1();
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}
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}
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stdio::drop_uart();
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println!("IRQ");
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loop {}
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}
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pub fn restart_core1() {
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let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new());
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CORE1_RESTART.store(true, Ordering::Relaxed);
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interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
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while CORE1_RESTART.load(Ordering::Relaxed) {
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asm::wfe();
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}
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}
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#[no_mangle]
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#[no_mangle]
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pub fn main_core0() {
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pub fn main_core0() {
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// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
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// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
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println!("\nzc706 main");
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println!("\nzc706 main");
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let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new());
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interrupt_controller.enable_interrupts();
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// ps7_init::apply();
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// ps7_init::apply();
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libboard_zynq::stdio::drop_uart();
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libboard_zynq::stdio::drop_uart();
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@ -147,12 +191,9 @@ pub fn main_core0() {
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let core1_req = unsafe { &mut CORE1_REQ.0 };
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let core1_req = unsafe { &mut CORE1_REQ.0 };
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let core1_res = unsafe { &mut CORE1_RES.1 };
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let core1_res = unsafe { &mut CORE1_RES.1 };
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let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new());
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interrupt_controller.enable_interrupts();
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task::block_on(async {
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task::block_on(async {
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for i in 0..10 {
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for i in 0..10 {
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// this interrupt would cause core1 to reset.
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restart_core1();
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interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
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core1_req.async_send(i).await;
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core1_req.async_send(i).await;
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let j = core1_res.async_recv().await;
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let j = core1_res.async_recv().await;
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println!("{} -> {}", i, j);
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println!("{} -> {}", i, j);
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@ -9,8 +9,9 @@ edition = "2018"
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target_zc706 = ["libboard_zynq/target_zc706"]
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target_zc706 = ["libboard_zynq/target_zc706"]
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target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10"]
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target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10"]
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panic_handler = []
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panic_handler = []
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dummy_irq_handler = []
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default = ["panic_handler"]
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default = ["panic_handler", "dummy_irq_handler"]
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[dependencies]
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[dependencies]
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r0 = "1"
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r0 = "1"
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@ -1,12 +1,6 @@
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use libregister::{RegisterR, RegisterW};
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use libregister::RegisterR;
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use libcortex_a9::regs::{DFSR, MPIDR, SP};
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use libcortex_a9::regs::{DFSR, MPIDR};
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use libcortex_a9::asm;
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use libboard_zynq::{println, stdio};
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use libboard_zynq::{println, stdio, gic, mpcore};
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extern "C" {
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fn main_core1();
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static mut __stack1_start: u32;
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}
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#[link_section = ".text.boot"]
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#[link_section = ".text.boot"]
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#[no_mangle]
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#[no_mangle]
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@ -59,19 +53,8 @@ pub unsafe extern "C" fn ReservedException() {
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#[link_section = ".text.boot"]
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#[link_section = ".text.boot"]
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#[no_mangle]
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#[no_mangle]
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#[naked]
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#[naked]
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#[cfg(feature = "dummy_irq_handler")]
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pub unsafe extern "C" fn IRQ() {
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pub unsafe extern "C" fn IRQ() {
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if MPIDR.read().cpu_id() == 1{
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let mpcore = mpcore::RegisterBlock::new();
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let mut gic = gic::InterruptController::new(mpcore);
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let id = gic.get_interrupt_id();
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if id.0 == 0 {
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gic.end_interrupt(id);
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asm::exit_irq();
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SP.write(&mut __stack1_start as *mut _ as u32);
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asm::enable_irq();
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main_core1();
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}
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}
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stdio::drop_uart();
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stdio::drop_uart();
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println!("IRQ");
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println!("IRQ");
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loop {}
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loop {}
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