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zynq-rs
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README: add introduction

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Sebastien Bourdeauducq 2020-09-29 16:27:44 +08:00
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README.md
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@ -1,4 +1,23 @@
# Build # Bare-metal Rust on Zynq-7000
Supported features:
* Clocking setup
* UART
* SDRAM setup
* Ethernet with smoltcp and async-await on TCP sockets
* SD card
* PL programming and startup
* Pure Rust SZL first-stage bootloader, with SD boot and netboot
* Control of second CPU core and message passing, with async-await support
Supported boards:
* ZC706
* Red Pitaya (note: SDRAM issues, worked around using `ps7_init`)
* Cora Z7-10 (note: SDRAM issues)
## Build
```shell ```shell
nix-shell --command "cargo xbuild --release -p experiments" nix-shell --command "cargo xbuild --release -p experiments"
@ -6,9 +25,9 @@ nix-shell --command "cargo xbuild --release -p experiments"
Currently the ELF output is placed at `target/armv7-none-eabihf/release/experiments` Currently the ELF output is placed at `target/armv7-none-eabihf/release/experiments`
# Debug ## Debug
## Running on the ZC706 ### Running on the ZC706
```shell ```shell
nix-shell --command "cargo xbuild --release -p experiments" nix-shell --command "cargo xbuild --release -p experiments"
@ -16,7 +35,7 @@ cd openocd
openocd -f zc706.cfg openocd -f zc706.cfg
``` ```
## Running on the Cora Z7-10 ### Running on the Cora Z7-10
```shell ```shell
nix-shell --command "cd experiments && cargo xbuild --release --no-default-features --features=target_cora_z7_10" nix-shell --command "cd experiments && cargo xbuild --release --no-default-features --features=target_cora_z7_10"
@ -24,7 +43,7 @@ cd openocd
openocd -f cora-z7-10.cfg openocd -f cora-z7-10.cfg
``` ```
## Loading a bitstream into volatile memory ### Loading a bitstream into volatile memory
```shell ```shell
openocd -f zc706.cfg -c "pld load 0 blinker_migen.bit; exit" openocd -f zc706.cfg -c "pld load 0 blinker_migen.bit; exit"