forked from M-Labs/zynq-rs
openocd: moved common code from target files
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e96222ff6f
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@ -0,0 +1,20 @@
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set XC7_JSHUTDOWN 0x0d
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set XC7_JPROGRAM 0x0b
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set XC7_JSTART 0x0c
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set XC7_BYPASS 0x3f
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proc xc7_program {tap} {
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global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
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irscan $tap $XC7_JSHUTDOWN
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irscan $tap $XC7_JPROGRAM
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runtest 60000
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#JSTART prevents this from working...
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#irscan $tap $XC7_JSTART
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runtest 2000
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irscan $tap $XC7_BYPASS
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runtest 2000
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}
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pld device virtex2 zynq.tap 1
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init
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xc7_program zynq.tap
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@ -8,26 +8,7 @@ source ./zynq-7000.cfg
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reset_config srst_only srst_push_pull
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set XC7_JSHUTDOWN 0x0d
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set XC7_JPROGRAM 0x0b
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set XC7_JSTART 0x0c
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set XC7_BYPASS 0x3f
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proc xc7_program {tap} {
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global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
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irscan $tap $XC7_JSHUTDOWN
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irscan $tap $XC7_JPROGRAM
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runtest 60000
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#JSTART prevents this from working...
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#irscan $tap $XC7_JSTART
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runtest 2000
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irscan $tap $XC7_BYPASS
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runtest 2000
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}
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pld device virtex2 zynq.tap 1
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init
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xc7_program zynq.tap
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source ./common.cfg
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reset halt
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@ -17,26 +17,7 @@ reset_config srst_only srst_open_drain
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adapter srst pulse_width 250
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adapter srst delay 400
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set XC7_JSHUTDOWN 0x0d
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set XC7_JPROGRAM 0x0b
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set XC7_JSTART 0x0c
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set XC7_BYPASS 0x3f
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proc xc7_program {tap} {
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global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
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irscan $tap $XC7_JSHUTDOWN
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irscan $tap $XC7_JPROGRAM
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runtest 60000
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#JSTART prevents this from working...
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#irscan $tap $XC7_JSTART
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runtest 2000
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irscan $tap $XC7_BYPASS
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runtest 2000
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}
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pld device virtex2 zynq.tap 1
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init
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xc7_program zynq.tap
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source ./common.cfg
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reset halt
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@ -8,26 +8,7 @@ source ./zynq-7000.cfg
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reset_config none
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set XC7_JSHUTDOWN 0x0d
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set XC7_JPROGRAM 0x0b
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set XC7_JSTART 0x0c
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set XC7_BYPASS 0x3f
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proc xc7_program {tap} {
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global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
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irscan $tap $XC7_JSHUTDOWN
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irscan $tap $XC7_JPROGRAM
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runtest 60000
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#JSTART prevents this from working...
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#irscan $tap $XC7_JSTART
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runtest 2000
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irscan $tap $XC7_BYPASS
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runtest 2000
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}
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pld device virtex2 zynq.tap 1
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init
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xc7_program zynq.tap
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source ./common.cfg
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halt
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@ -10,26 +10,7 @@ reset_config srst_only srst_open_drain
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adapter srst pulse_width 250
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adapter srst delay 400
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set XC7_JSHUTDOWN 0x0d
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set XC7_JPROGRAM 0x0b
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set XC7_JSTART 0x0c
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set XC7_BYPASS 0x3f
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proc xc7_program {tap} {
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global XC7_JSHUTDOWN XC7_JPROGRAM XC7_JSTART XC7_BYPASS
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irscan $tap $XC7_JSHUTDOWN
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irscan $tap $XC7_JPROGRAM
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runtest 60000
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#JSTART prevents this from working...
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#irscan $tap $XC7_JSTART
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runtest 2000
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irscan $tap $XC7_BYPASS
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runtest 2000
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}
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pld device virtex2 zynq.tap 1
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init
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xc7_program zynq.tap
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source ./common.cfg
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reset halt
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