forked from M-Labs/zynq-rs
uart: extend regs
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@ -3,9 +3,9 @@ use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, register_at, regs::*};
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use crate::{register, register_bit, register_bits, register_at, regs::*};
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pub enum ChannelMode {
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pub enum ChannelMode {
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Normal = 0b00,
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Normal = 0b00,
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AutomaticEcho = 0b01,
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AutomaticEcho = 0b01,
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LocalLoopback = 0b10,
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LocalLoopback = 0b10,
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RemoteLoopback = 0b11,
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RemoteLoopback = 0b11,
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}
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}
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@ -14,9 +14,14 @@ pub enum ParityMode {
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OddParity = 0b001,
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OddParity = 0b001,
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ForceTo0 = 0b010,
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ForceTo0 = 0b010,
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ForceTo1 = 0b011,
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ForceTo1 = 0b011,
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None = 0b111,
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None = 0b100,
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}
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}
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pub enum StopBits {
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One = 0b00,
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OneAndHalf = 0b01,
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Two = 0b10,
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}
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#[repr(C)]
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#[repr(C)]
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pub struct RegisterBlock {
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pub struct RegisterBlock {
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@ -56,7 +61,14 @@ register_bit!(control, stpbrk, 8);
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register!(mode, Mode, RW, u32);
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register!(mode, Mode, RW, u32);
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/// Channel mode: Defines the mode of operation of the UART.
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/// Channel mode: Defines the mode of operation of the UART.
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register_bits!(mode, chmode, u8, 8, 9);
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register_bits!(mode, chmode, u8, 8, 9);
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/// Number of stop bits
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register_bits!(mode, nbstop, u8, 6, 7);
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/// Parity type select
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register_bits!(mode, par, u8, 3, 5);
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register_bits!(mode, par, u8, 3, 5);
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/// Character length select
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register_bits!(mode, chrl, u8, 1, 2);
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/// Clock source select
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register_bit!(mode, clks, 0);
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register!(baud_rate_gen, BaudRateGen, RW, u32);
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register!(baud_rate_gen, BaudRateGen, RW, u32);
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register_bits!(baud_rate_gen, cd, u16, 0, 15);
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register_bits!(baud_rate_gen, cd, u16, 0, 15);
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