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zynq-rs
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libsupport_zynq/boot: enable FPU on boot

This commit is contained in:
pca006132 2021-01-15 12:00:35 +08:00
parent 2c6cc58c07
commit 5923a66512
2 changed files with 2 additions and 3 deletions
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3
libsupport_zynq/src/boot.rs
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@ -4,7 +4,7 @@ use libregister::{
VolatileCell, VolatileCell,
RegisterR, RegisterW, RegisterRW, RegisterR, RegisterW, RegisterRW,
}; };
use libcortex_a9::{asm, l2c, regs::*, cache, mmu, spin_lock_yield, notify_spin_lock}; use libcortex_a9::{asm, l2c, regs::*, cache, mmu, spin_lock_yield, notify_spin_lock, enable_fpu};
use libboard_zynq::{slcr, mpcore}; use libboard_zynq::{slcr, mpcore};
extern "C" { extern "C" {
@ -43,6 +43,7 @@ pub unsafe extern "C" fn Reset() -> ! {
unsafe fn boot_core0() -> ! { unsafe fn boot_core0() -> ! {
l1_cache_init(); l1_cache_init();
enable_fpu();
let mpcore = mpcore::RegisterBlock::mpcore(); let mpcore = mpcore::RegisterBlock::mpcore();
mpcore.scu_invalidate.invalidate_all_cores(); mpcore.scu_invalidate.invalidate_all_cores();

2
szl/src/main.rs
View File

@ -20,7 +20,6 @@ use libconfig::{bootgen, sd_reader, Config};
use libcortex_a9::{ use libcortex_a9::{
asm::{dsb, isb}, asm::{dsb, isb},
cache::{bpiall, dcciall, iciallu}, cache::{bpiall, dcciall, iciallu},
enable_fpu,
l2c::enable_l2_cache, l2c::enable_l2_cache,
}; };
use libregister::RegisterR; use libregister::RegisterR;
@ -66,7 +65,6 @@ fn boot_sd<File: Read + Seek>(
#[no_mangle] #[no_mangle]
pub fn main_core0() { pub fn main_core0() {
GlobalTimer::start(); GlobalTimer::start();
enable_fpu();
logger::init().unwrap(); logger::init().unwrap();
log::set_max_level(log::LevelFilter::Debug); log::set_max_level(log::LevelFilter::Debug);
println!( println!(