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zynq-rs
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core1: reset -> disable, add restart function

This commit is contained in:
Sebastien Bourdeauducq 2020-04-17 14:05:45 +08:00
parent bcedd02ad9
commit 50667f0a13
2 changed files with 15 additions and 12 deletions
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2
experiments/src/main.rs
View File

@ -151,7 +151,7 @@ pub fn main_core0() {
println!("{} -> {}", i, j); println!("{} -> {}", i, j);
} }
}); });
core1.reset(); core1.disable();
libcortex_a9::asm::dsb(); libcortex_a9::asm::dsb();
print!("Core1 stack [{:08X}..{:08X}]:", &core1.stack[0] as *const _ as u32, &core1.stack[core1.stack.len() - 1] as *const _ as u32); print!("Core1 stack [{:08X}..{:08X}]:", &core1.stack[0] as *const _ as u32, &core1.stack[core1.stack.len() - 1] as *const _ as u32);

25
libsupport_zynq/src/boot.rs
View File

@ -109,17 +109,6 @@ pub struct Core1<S: AsMut<[u32]>> {
} }
impl<S: AsMut<[u32]>> Core1<S> { impl<S: AsMut<[u32]>> Core1<S> {
pub fn reset(&self) {
unsafe {
CORE1_STACK.set(0);
}
slcr::RegisterBlock::unlocked(|slcr| {
slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(true));
slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
});
}
/// Reset and start core1 /// Reset and start core1
/// ///
/// The stack must not be in OCM because core1 still has to /// The stack must not be in OCM because core1 still has to
@ -152,4 +141,18 @@ impl<S: AsMut<[u32]>> Core1<S> {
core core
} }
pub fn disable(&self) {
unsafe {
CORE1_STACK.set(0);
}
self.restart();
}
pub fn restart(&self) {
slcr::RegisterBlock::unlocked(|slcr| {
slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(true));
slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
});
}
} }