forked from M-Labs/zynq-rs
core1: support redirecting vectors to sdram
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ce844f1b02
commit
4e1f46b3e2
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@ -113,7 +113,7 @@ pub fn main_core0() {
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flash = flash_io.stop();
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flash = flash_io.stop();
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}
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}
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let core1 = boot::Core1::start();
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let core1 = boot::Core1::start(false);
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let (mut core1_req, rx) = sync_channel(10);
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let (mut core1_req, rx) = sync_channel(10);
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*CORE1_REQ.lock() = Some(rx);
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*CORE1_REQ.lock() = Some(rx);
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@ -1,4 +1,5 @@
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use r0::zero_bss;
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use r0::zero_bss;
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use core::ptr::write_volatile;
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use libregister::{
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use libregister::{
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VolatileCell,
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VolatileCell,
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RegisterR, RegisterW, RegisterRW,
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RegisterR, RegisterW, RegisterRW,
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@ -108,7 +109,7 @@ pub struct Core1 {
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impl Core1 {
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impl Core1 {
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/// Reset and start core1
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/// Reset and start core1
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pub fn start() -> Self {
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pub fn start(sdram: bool) -> Self {
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// reset and stop (safe to repeat)
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// reset and stop (safe to repeat)
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(true));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(true));
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@ -116,13 +117,27 @@ impl Core1 {
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
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});
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});
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if sdram {
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// Cores always start from OCM no matter what you do.
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// Make up a vector table there that just jumps to SDRAM.
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for i in 0..8 {
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unsafe {
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// this is the ARM instruction "b +0x00100000"
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write_volatile((i*4) as *mut u32, 0xea03fffe);
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}
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}
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}
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unsafe {
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unsafe {
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CORE1_ENABLED.set(true);
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CORE1_ENABLED.set(true);
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}
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}
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// Ensure stack pointer has been written to cache
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// Ensure values have been written to cache
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asm::dmb();
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asm::dmb();
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// Flush cache-line
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// Flush cache-line
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cache::dccmvac(unsafe { &CORE1_ENABLED } as *const _ as usize);
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cache::dccmvac(unsafe { &CORE1_ENABLED } as *const _ as usize);
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if sdram {
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cache::dccmvac(0);
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}
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// wake up core1
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// wake up core1
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr::RegisterBlock::unlocked(|slcr| {
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