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libcortex_a9: migrate from asm! to llvm_asm! to avoid future breakage

This commit is contained in:
Astro 2020-05-01 01:11:35 +02:00
parent 008a995429
commit 2c756ba32e
4 changed files with 18 additions and 18 deletions
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12
libcortex_a9/src/asm.rs
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@ -1,35 +1,35 @@
/// The classic no-op /// The classic no-op
#[inline] #[inline]
pub fn nop() { pub fn nop() {
unsafe { asm!("nop" :::: "volatile") } unsafe { llvm_asm!("nop" :::: "volatile") }
} }
/// Wait For Event /// Wait For Event
#[inline] #[inline]
pub fn wfe() { pub fn wfe() {
unsafe { asm!("wfe" :::: "volatile") } unsafe { llvm_asm!("wfe" :::: "volatile") }
} }
/// Send Event /// Send Event
#[inline] #[inline]
pub fn sev() { pub fn sev() {
unsafe { asm!("sev" :::: "volatile") } unsafe { llvm_asm!("sev" :::: "volatile") }
} }
/// Data Memory Barrier /// Data Memory Barrier
#[inline] #[inline]
pub fn dmb() { pub fn dmb() {
unsafe { asm!("dmb" :::: "volatile") } unsafe { llvm_asm!("dmb" :::: "volatile") }
} }
/// Data Synchronization Barrier /// Data Synchronization Barrier
#[inline] #[inline]
pub fn dsb() { pub fn dsb() {
unsafe { asm!("dsb" :::: "volatile") } unsafe { llvm_asm!("dsb" :::: "volatile") }
} }
/// Instruction Synchronization Barrier /// Instruction Synchronization Barrier
#[inline] #[inline]
pub fn isb() { pub fn isb() {
unsafe { asm!("isb" :::: "volatile") } unsafe { llvm_asm!("isb" :::: "volatile") }
} }

18
libcortex_a9/src/cache.rs
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@ -2,7 +2,7 @@
#[inline(always)] #[inline(always)]
pub fn tlbiall() { pub fn tlbiall() {
unsafe { unsafe {
asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile"); llvm_asm!("mcr p15, 0, $0, c8, c7, 0" :: "r" (0) :: "volatile");
} }
} }
@ -10,7 +10,7 @@ pub fn tlbiall() {
#[inline(always)] #[inline(always)]
pub fn iciallu() { pub fn iciallu() {
unsafe { unsafe {
asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile"); llvm_asm!("mcr p15, 0, $0, c7, c5, 0" :: "r" (0) :: "volatile");
} }
} }
@ -18,7 +18,7 @@ pub fn iciallu() {
#[inline(always)] #[inline(always)]
pub fn bpiall() { pub fn bpiall() {
unsafe { unsafe {
asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile"); llvm_asm!("mcr p15, 0, $0, c7, c5, 6" :: "r" (0) :: "volatile");
} }
} }
@ -26,7 +26,7 @@ pub fn bpiall() {
#[inline(always)] #[inline(always)]
pub fn dccsw(setway: u32) { pub fn dccsw(setway: u32) {
unsafe { unsafe {
asm!("mcr p15, 0, $0, c7, c10, 2" :: "r" (setway) :: "volatile"); llvm_asm!("mcr p15, 0, $0, c7, c10, 2" :: "r" (setway) :: "volatile");
} }
} }
@ -38,7 +38,7 @@ pub fn dcisw(setway: u32) {
// also see example code (for DCCISW, but DCISW will be // also see example code (for DCCISW, but DCISW will be
// analogous) "Example code for cache maintenance operations" // analogous) "Example code for cache maintenance operations"
// on pages B2-1286 and B2-1287. // on pages B2-1286 and B2-1287.
asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile"); llvm_asm!("mcr p15, 0, $0, c7, c6, 2" :: "r" (setway) :: "volatile");
} }
} }
@ -58,7 +58,7 @@ pub fn dciall() {
// select L1 data cache // select L1 data cache
unsafe { unsafe {
asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile"); llvm_asm!("mcr p15, 2, $0, c0, c0, 0" :: "r" (0) :: "volatile");
} }
// Invalidate entire D-Cache by iterating every set and every way // Invalidate entire D-Cache by iterating every set and every way
@ -101,7 +101,7 @@ fn slice_cache_line_addrs<T>(slice: &[T]) -> impl Iterator<Item = usize> {
#[inline(always)] #[inline(always)]
pub fn dccimvac(addr: usize) { pub fn dccimvac(addr: usize) {
unsafe { unsafe {
asm!("mcr p15, 0, $0, c7, c14, 1" :: "r" (addr) :: "volatile"); llvm_asm!("mcr p15, 0, $0, c7, c14, 1" :: "r" (addr) :: "volatile");
} }
} }
@ -122,7 +122,7 @@ pub fn dcci_slice<T>(slice: &mut [T]) {
#[inline(always)] #[inline(always)]
pub fn dccmvac(addr: usize) { pub fn dccmvac(addr: usize) {
unsafe { unsafe {
asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile"); llvm_asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile");
} }
} }
@ -148,7 +148,7 @@ pub fn dcc_slice<T>(slice: &[T]) {
/// affecting more data than intended. /// affecting more data than intended.
#[inline(always)] #[inline(always)]
pub unsafe fn dcimvac(addr: usize) { pub unsafe fn dcimvac(addr: usize) {
asm!("mcr p15, 0, $0, c7, c6, 1" :: "r" (addr) :: "volatile"); llvm_asm!("mcr p15, 0, $0, c7, c6, 1" :: "r" (addr) :: "volatile");
} }
/// Data cache clean and invalidate for an object. /// Data cache clean and invalidate for an object.

2
libcortex_a9/src/lib.rs
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@ -1,5 +1,5 @@
#![no_std] #![no_std]
#![feature(asm, global_asm)] #![feature(llvm_asm, global_asm)]
#![feature(never_type)] #![feature(never_type)]
extern crate alloc; extern crate alloc;

4
libcortex_a9/src/regs.rs
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@ -11,7 +11,7 @@ macro_rules! def_reg_r {
#[inline] #[inline]
fn read(&self) -> Self::R { fn read(&self) -> Self::R {
let mut value: u32; let mut value: u32;
unsafe { asm!($asm_instr : "=r" (value) ::: "volatile") } unsafe { llvm_asm!($asm_instr : "=r" (value) ::: "volatile") }
value.into() value.into()
} }
} }
@ -26,7 +26,7 @@ macro_rules! def_reg_w {
#[inline] #[inline]
fn write(&mut self, value: Self::W) { fn write(&mut self, value: Self::W) {
let value: u32 = value.into(); let value: u32 = value.into();
unsafe { asm!($asm_instr :: "r" (value) :: "volatile") } unsafe { llvm_asm!($asm_instr :: "r" (value) :: "volatile") }
} }
#[inline] #[inline]