forked from M-Labs/zynq-rs
Changes usage of sev/wfe to spinlock functions.
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parent
9e97102e12
commit
25c6d5eeaa
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@ -30,6 +30,7 @@ use libcortex_a9::{
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sync_channel::{Sender, Receiver},
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sync_channel,
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regs::{MPIDR, SP},
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spin_lock_yield, notify_spin_lock,
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asm
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};
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use libregister::{RegisterR, RegisterW};
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@ -64,7 +65,7 @@ pub unsafe extern "C" fn IRQ() {
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SP.write(&mut __stack1_start as *mut _ as u32);
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asm::enable_irq();
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CORE1_RESTART.store(false, Ordering::Relaxed);
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asm::sev();
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notify_spin_lock();
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main_core1();
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}
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}
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@ -78,7 +79,7 @@ pub fn restart_core1() {
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CORE1_RESTART.store(true, Ordering::Relaxed);
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interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
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while CORE1_RESTART.load(Ordering::Relaxed) {
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asm::wfe();
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spin_lock_yield();
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}
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}
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@ -7,6 +7,7 @@ edition = "2018"
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[features]
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target_zc706 = []
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target_cora_z7_10 = []
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power_saving = []
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default = ["target_zc706"]
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[dependencies]
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@ -18,3 +18,19 @@ pub use uncached::UncachedSlice;
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pub use fpu::enable_fpu;
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global_asm!(include_str!("exceptions.s"));
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#[inline]
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pub fn spin_lock_yield() {
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#[cfg(feature = "power_saving")]
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asm::wfe();
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}
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#[inline]
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pub fn notify_spin_lock() {
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#[cfg(feature = "power_saving")]
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{
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asm::dsb();
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asm::sev();
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}
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}
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@ -1,20 +1,10 @@
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use core::ops::{Deref, DerefMut};
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use core::sync::atomic::{AtomicU32, Ordering};
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use core::cell::UnsafeCell;
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use super::asm::*;
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/// [Power-saving features](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/ch01s03s02.html)
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#[inline]
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fn wait_for_update() {
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wfe();
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}
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/// [Power-saving features](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/ch01s03s02.html)
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#[inline]
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fn signal_update() {
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dsb();
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sev();
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}
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use super::{
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spin_lock_yield, notify_spin_lock,
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asm::{dmb, enter_critical, exit_critical}
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};
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const LOCKED: u32 = 1;
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const UNLOCKED: u32 = 0;
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@ -45,7 +35,7 @@ impl<T> Mutex<T> {
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while self.locked.compare_and_swap(UNLOCKED, LOCKED, Ordering::Acquire) != UNLOCKED {
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unsafe {
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exit_critical(irq);
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wait_for_update();
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spin_lock_yield();
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irq = enter_critical();
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}
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}
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@ -68,7 +58,7 @@ impl<T> Mutex<T> {
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dmb();
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self.locked.store(UNLOCKED, Ordering::Release);
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signal_update();
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notify_spin_lock();
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}
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}
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@ -1,10 +1,10 @@
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use super::asm::{sev, wfe};
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use super::{spin_lock_yield, notify_spin_lock};
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use core::{
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task::{Context, Poll},
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pin::Pin,
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future::Future
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future::Future,
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sync::atomic::{AtomicI32, Ordering}
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};
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use core::sync::atomic::{AtomicI32, Ordering};
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pub struct Semaphore {
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value: AtomicI32,
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@ -31,7 +31,7 @@ impl Semaphore {
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pub fn wait(&self) {
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while self.try_wait().is_none() {
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wfe();
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spin_lock_yield();
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}
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}
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@ -59,7 +59,7 @@ impl Semaphore {
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let value = self.value.load(Ordering::Relaxed);
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if value < self.max {
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if self.value.compare_and_swap(value, value + 1, Ordering::SeqCst) == value {
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sev();
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notify_spin_lock();
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return;
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}
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} else {
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@ -6,7 +6,7 @@ use core::{
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task::{Context, Poll},
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};
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use alloc::boxed::Box;
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use super::asm::*;
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use super::{spin_lock_yield, notify_spin_lock};
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pub struct Sender<'a, T> where T: Clone {
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list: &'a [AtomicPtr<T>],
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@ -35,9 +35,7 @@ impl<'a, T> Sender<'a, T> where T: Clone {
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let prev = entry.swap(ptr, Ordering::Relaxed);
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// we allow other end get it first
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self.write.store((write + 1) % self.list.len(), Ordering::Release);
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// wake up other core, actually I wonder if the dsb is really needed...
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dsb();
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sev();
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notify_spin_lock();
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if !prev.is_null() {
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unsafe {
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drop_in_place(prev);
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@ -51,7 +49,7 @@ impl<'a, T> Sender<'a, T> where T: Clone {
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let mut content = content;
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while let Err(back) = self.try_send(content) {
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content = back;
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wfe();
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spin_lock_yield();
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}
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}
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@ -116,9 +114,7 @@ impl<'a, T> Receiver<'a, T> where T: Clone {
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};
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let result = data.clone();
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self.read.store((read + 1) % self.list.len(), Ordering::Release);
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// wake up other core, still idk if the dsb is needed...
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dsb();
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sev();
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notify_spin_lock();
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Ok(result)
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}
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}
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@ -128,7 +124,7 @@ impl<'a, T> Receiver<'a, T> where T: Clone {
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if let Ok(data) = self.try_recv() {
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return data;
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}
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wfe();
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spin_lock_yield();
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}
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}
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@ -4,7 +4,7 @@ use libregister::{
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VolatileCell,
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RegisterR, RegisterW, RegisterRW,
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};
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use libcortex_a9::{asm, regs::*, cache, mmu};
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use libcortex_a9::{asm, regs::*, cache, mmu, spin_lock_yield, notify_spin_lock};
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use libboard_zynq::{slcr, mpcore};
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extern "C" {
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@ -29,7 +29,7 @@ pub unsafe extern "C" fn Reset() -> ! {
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}
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1 => {
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while !CORE1_ENABLED.get() {
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asm::wfe();
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spin_lock_yield();
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}
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SP.write(&mut __stack1_start as *mut _ as u32);
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boot_core1();
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@ -144,6 +144,7 @@ impl Core1 {
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(false));
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});
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notify_spin_lock();
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Core1 {}
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}
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