forked from M-Labs/zynq-rs
libboard_zynq: make RegisterBlock constructors more consistent
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36947104e3
commit
1a96a7550a
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@ -56,7 +56,7 @@ static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
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#[naked]
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pub unsafe extern "C" fn IRQ() {
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if MPIDR.read().cpu_id() == 1{
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let mpcore = mpcore::RegisterBlock::new();
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let mpcore = mpcore::RegisterBlock::mpcore();
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let mut gic = gic::InterruptController::gic(mpcore);
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let id = gic.get_interrupt_id();
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if id.0 == 0 {
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@ -75,7 +75,7 @@ pub unsafe extern "C" fn IRQ() {
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}
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pub fn restart_core1() {
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let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::new());
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let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
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CORE1_RESTART.store(true, Ordering::Relaxed);
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interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
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while CORE1_RESTART.load(Ordering::Relaxed) {
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@ -87,7 +87,7 @@ pub fn restart_core1() {
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pub fn main_core0() {
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// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
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println!("\nzc706 main");
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let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::new());
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let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
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interrupt_controller.enable_interrupts();
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// ps7_init::apply();
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libboard_zynq::stdio::drop_uart();
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@ -97,7 +97,7 @@ pub fn main_core0() {
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info!(
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"Boot mode: {:?}",
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zynq::slcr::RegisterBlock::new()
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zynq::slcr::RegisterBlock::slcr()
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.boot_mode
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.read()
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.boot_mode_pins()
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@ -331,7 +331,7 @@ static DONE: Mutex<bool> = Mutex::new(false);
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#[no_mangle]
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pub fn main_core1() {
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println!("Hello from core1!");
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let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::new());
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let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore());
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interrupt_controller.enable_interrupts();
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let req = unsafe { &mut CORE1_REQ.1 };
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let res = unsafe { &mut CORE1_RES.0 };
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@ -14,7 +14,7 @@ enum CpuClockMode {
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impl CpuClockMode {
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pub fn get() -> Self {
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let regs = slcr::RegisterBlock::new();
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let regs = slcr::RegisterBlock::slcr();
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if regs.clk_621_true.read().clk_621_true() {
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CpuClockMode::C621
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} else {
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@ -59,7 +59,7 @@ impl Clocks {
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}
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pub fn cpu_6x4x(&self) -> u32 {
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let slcr = slcr::RegisterBlock::new();
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let slcr = slcr::RegisterBlock::slcr();
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let arm_clk_ctrl = slcr.arm_clk_ctrl.read();
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let pll = match arm_clk_ctrl.srcsel() {
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ArmPllSource::ArmPll => self.arm,
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@ -92,7 +92,7 @@ impl Clocks {
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}
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pub fn uart_ref_clk(&self) -> u32 {
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let regs = slcr::RegisterBlock::new();
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let regs = slcr::RegisterBlock::slcr();
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let uart_clk_ctrl = regs.uart_clk_ctrl.read();
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let pll = match uart_clk_ctrl.srcsel() {
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slcr::PllSource::ArmPll =>
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@ -106,7 +106,7 @@ impl Clocks {
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}
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pub fn sdio_ref_clk(&self) -> u32 {
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let regs = slcr::RegisterBlock::new();
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let regs = slcr::RegisterBlock::slcr();
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let sdio_clk_ctrl = regs.sdio_clk_ctrl.read();
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let pll = match sdio_clk_ctrl.srcsel() {
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slcr::PllSource::ArmPll =>
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@ -44,7 +44,7 @@ pub trait ClockSource {
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/// get configured frequency
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fn freq() -> u32 {
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let mut slcr = slcr::RegisterBlock::new();
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let mut slcr = slcr::RegisterBlock::slcr();
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let (pll_ctrl, _, _) = Self::pll_regs(&mut slcr);
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u32::from(pll_ctrl.read().pll_fdiv()) * PS_CLK
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}
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@ -27,7 +27,7 @@ impl DdrRam {
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Self::calibrate_iob_impedance(&clocks);
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Self::configure_iob();
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let regs = unsafe { regs::RegisterBlock::new() };
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let regs = unsafe { regs::RegisterBlock::ddrc() };
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let mut ddr = DdrRam { regs };
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ddr.configure();
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ddr.reset_ddrc();
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@ -1,6 +1,6 @@
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use volatile_register::{RO, RW};
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use libregister::{register, register_bit, register_bits, register_bits_typed};
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use libregister::{register, register_at, register_bit, register_bits, register_bits_typed};
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#[allow(unused)]
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#[derive(Clone, Copy)]
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@ -158,11 +158,7 @@ pub struct RegisterBlock {
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pub lpddr_ctrl3: RW<u32>,
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}
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impl RegisterBlock {
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pub unsafe fn new() -> &'static mut Self {
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&mut *(0xF8006000 as *mut _)
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}
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}
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register_at!(RegisterBlock, 0xF8006000, ddrc);
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register!(ddrc_ctrl, DdrcCtrl, RW, u32);
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register_bit!(ddrc_ctrl,
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@ -1,6 +1,6 @@
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use volatile_register::{RO, WO, RW};
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use libregister::{register, register_bit, register_bits, register_bits_typed};
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use libregister::{register, register_at, register_bit, register_bits, register_bits_typed};
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#[repr(C)]
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pub struct RegisterBlock {
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@ -110,18 +110,8 @@ pub struct RegisterBlock {
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pub design_cfg5: RO<u32>,
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}
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impl RegisterBlock {
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const GEM0: *mut Self = 0xE000B000 as *mut _;
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const GEM1: *mut Self = 0xE000C000 as *mut _;
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pub fn gem0() -> &'static mut Self {
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unsafe { &mut *Self::GEM0 }
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}
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pub fn gem1() -> &'static mut Self {
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unsafe { &mut *Self::GEM1 }
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}
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}
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register_at!(RegisterBlock, 0xE000B000, gem0);
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register_at!(RegisterBlock, 0xE000C000, gem1);
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register!(net_ctrl, NetCtrl, RW, u32);
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register_bit!(net_ctrl, loopback_local, 1);
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@ -1,6 +1,6 @@
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use volatile_register::{RO, WO, RW};
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use libregister::{register, register_bit, register_bits};
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use libregister::{register, register_at, register_bit, register_bits};
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#[repr(C)]
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pub struct RegisterBlock {
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@ -30,13 +30,9 @@ pub struct RegisterBlock {
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pub mod_id: RW<u32>,
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}
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impl RegisterBlock {
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const BASE_ADDRESS: *mut Self = 0xE000D000 as *mut _;
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const BASE_ADDRESS: u32 = 0xE000D000;
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pub fn qspi() -> &'static mut Self {
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unsafe { &mut *Self::BASE_ADDRESS }
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}
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}
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register_at!(RegisterBlock, 0xE000D000, qspi);
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register!(config, Config, RW, u32);
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register_bit!(config,
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@ -8,7 +8,7 @@ use embedded_hal::timer::CountDown;
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use libregister::{RegisterR, RegisterRW, RegisterW};
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pub struct I2c {
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regs: regs::RegisterWrapper,
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regs: regs::RegisterBlock,
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count_down: super::timer::global::CountDown<Microseconds>
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}
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@ -43,7 +43,7 @@ impl I2c {
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fn i2c_common(gpio_output_mask: u16) -> Self {
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// Setup register block
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let self_ = Self {
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regs: regs::RegisterWrapper::new(),
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regs: regs::RegisterBlock::i2c(),
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count_down: unsafe { super::timer::GlobalTimer::get() }.countdown()
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};
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@ -21,15 +21,15 @@ use libregister::{
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// Current compatibility:
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// zc706: GPIO 50, 51 == SCL, SDA
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pub struct RegisterWrapper {
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pub struct RegisterBlock {
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pub gpio_output_mask: &'static mut GPIOOutputMask,
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pub gpio_input: &'static mut GPIOInput,
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pub gpio_direction: &'static mut GPIODirection,
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pub gpio_output_enable: &'static mut GPIOOutputEnable,
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}
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impl RegisterWrapper {
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pub fn new() -> Self {
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impl RegisterBlock {
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pub fn i2c() -> Self {
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Self {
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gpio_output_mask: GPIOOutputMask::new(),
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gpio_input: GPIOInput::new(),
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@ -138,7 +138,7 @@ pub struct RegisterBlock {
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pub icdsgir: ICDSGIR,
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}
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register_at!(RegisterBlock, 0xF8F00000, new);
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register_at!(RegisterBlock, 0xF8F00000, mpcore);
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register!(value_register, ValueRegister, RW, u32);
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register_bits!(value_register, value, u32, 0, 31);
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@ -253,12 +253,12 @@ pub struct RegisterBlock {
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pub ddriob_dci_ctrl: DdriobDciCtrl,
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pub ddriob_dci_status: DdriobDciStatus,
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}
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register_at!(RegisterBlock, 0xF8000000, new);
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register_at!(RegisterBlock, 0xF8000000, slcr);
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impl RegisterBlock {
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/// Required to modify any sclr register
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pub fn unlocked<F: FnMut(&mut Self) -> R, R>(mut f: F) -> R {
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let mut self_ = Self::new();
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let mut self_ = Self::slcr();
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self_.slcr_unlock.unlock();
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let r = f(&mut self_);
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self_.slcr_lock.lock();
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@ -16,13 +16,13 @@ pub struct GlobalTimer {
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impl GlobalTimer {
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/// Get the potentially uninitialized timer
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pub unsafe fn get() -> GlobalTimer {
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let regs = mpcore::RegisterBlock::new();
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let regs = mpcore::RegisterBlock::mpcore();
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GlobalTimer { regs }
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}
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/// Get the timer with a reset
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pub fn start() -> GlobalTimer {
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let mut regs = mpcore::RegisterBlock::new();
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let mut regs = mpcore::RegisterBlock::mpcore();
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Self::reset(&mut regs);
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GlobalTimer { regs }
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}
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@ -43,7 +43,7 @@ pub unsafe extern "C" fn Reset() -> ! {
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unsafe fn boot_core0() -> ! {
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l1_cache_init();
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let mpcore = mpcore::RegisterBlock::new();
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let mpcore = mpcore::RegisterBlock::mpcore();
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mpcore.scu_invalidate.invalidate_all_cores();
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zero_bss(&mut __bss_start, &mut __bss_end);
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@ -68,7 +68,7 @@ unsafe fn boot_core0() -> ! {
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unsafe fn boot_core1() -> ! {
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l1_cache_init();
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let mpcore = mpcore::RegisterBlock::new();
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let mpcore = mpcore::RegisterBlock::mpcore();
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mpcore.scu_invalidate.invalidate_core1();
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let mmu_table = mmu::L1Table::get();
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