forked from M-Labs/zynq-rs
230 lines
6.0 KiB
Rust
230 lines
6.0 KiB
Rust
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//! I2C Bit-banging Controller
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mod regs;
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use log::{error, info, warn};
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use crate::{print, println};
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use super::clocks::Clocks;
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use super::slcr;
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use super::time::Microseconds;
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use embedded_hal::timer::CountDown;
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use libregister::{RegisterR, RegisterRW, RegisterW};
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const INVALID_BUS: &'static str = "Invalid I2C bus";
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pub struct I2C {
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regs: regs::RegisterBlock,
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count_down: super::timer::global::CountDown<Microseconds>
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}
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impl I2C {
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#[cfg(feature = "target_zc706")]
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pub fn i2c() -> Self {
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// Route I2C 0 SCL / SDA Signals to MIO Pins 50 / 51
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slcr::RegisterBlock::unlocked(|slcr| {
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// SCL
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slcr.mio_pin_50.write(
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slcr::MioPin50::zeroed()
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.l3_sel(0b000) // GPIO 50
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.io_type(slcr::IoBufferType::Lvcmos25)
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.pullup(true)
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);
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// SDA
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slcr.mio_pin_51.write(
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slcr::MioPin51::zeroed()
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.l3_sel(0b00) // GPIO 51
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.io_type(slcr::IoBufferType::Lvcmos25)
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.pullup(true)
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);
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});
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Self::ctor_common()
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}
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fn ctor_common() -> Self {
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// Setup register block
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let clocks = Clocks::get();
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let mut self_ = Self {
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regs: unsafe { regs::RegisterBlock::new() },
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count_down: unsafe { super::timer::GlobalTimer::get() }.countdown()
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};
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// Setup GPIO output mask
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self_.regs.gpio_output_mask.modify(|_, w| {
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w.scl_m(true).sda_m(true)
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});
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self_.init();
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self_
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}
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/// Delay for I2C operations, simple wrapper for nb.
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fn delay(&mut self, us: u64) {
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self.count_down.start(Microseconds(us));
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nb::block!(self.count_down.wait()).unwrap();
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}
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fn half_period(&mut self) { self.delay(100) }
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fn sda_i(&mut self) -> bool {
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self.regs.gpio_input.read().sda()
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}
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fn scl_i(&mut self) -> bool {
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self.regs.gpio_input.read().scl()
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}
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fn sda_oe(&mut self, oe: bool) {
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self.regs.gpio_output_enable.modify(|_, w| {
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w.sda(oe)
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})
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}
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fn sda_o(&mut self, o: bool) {
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self.regs.gpio_output_mask.modify(|_, w| {
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w.sda_o(o)
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})
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}
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fn scl_oe(&mut self, oe: bool) {
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self.regs.gpio_output_enable.modify(|_, w| {
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w.scl(oe)
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})
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}
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fn scl_o(&mut self, o: bool) {
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self.regs.gpio_output_mask.modify(|_, w| {
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w.scl_o(o)
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})
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}
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pub fn init(&mut self) -> Result<(), &'static str> {
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self.scl_oe(false);
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self.sda_oe(false);
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self.scl_o(false);
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self.sda_o(false);
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// Check the I2C bus is ready
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self.half_period();
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self.half_period();
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if !self.sda_i() {
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// Try toggling SCL a few times
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for _bit in 0..8 {
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self.scl_oe(true);
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self.half_period();
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self.scl_oe(false);
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self.half_period();
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}
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}
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if !self.sda_i() {
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return Err("SDA is stuck low and doesn't get unstuck");
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}
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if !self.scl_i() {
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return Err("SCL is stuck low and doesn't get unstuck");
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}
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// postcondition: SCL and SDA high
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Ok(())
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}
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pub fn start(&mut self) -> Result<(), &'static str> {
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// precondition: SCL and SDA high
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if !self.scl_i() {
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return Err("SCL is stuck low and doesn't get unstuck");
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}
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if !self.sda_i() {
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return Err("SDA arbitration lost");
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}
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self.sda_oe(true);
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self.half_period();
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self.scl_oe(true);
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// postcondition: SCL and SDA low
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Ok(())
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}
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pub fn restart(&mut self) -> Result<(), &'static str> {
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// precondition SCL and SDA low
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self.sda_oe(false);
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self.half_period();
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self.scl_oe(false);
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self.half_period();
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self.start()?;
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// postcondition: SCL and SDA low
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Ok(())
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}
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pub fn stop(&mut self) -> Result<(), &'static str> {
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// precondition: SCL and SDA low
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self.half_period();
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self.scl_oe(false);
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self.half_period();
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self.sda_oe(false);
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self.half_period();
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if !self.sda_i() {
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return Err("SDA arbitration lost");
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}
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// postcondition: SCL and SDA high
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Ok(())
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}
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pub fn write(&mut self, data: u8) -> Result<bool, &'static str> {
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// precondition: SCL and SDA low
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// MSB first
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for bit in (0..8).rev() {
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self.sda_oe(data & (1 << bit) == 0);
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self.half_period();
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self.scl_o(false);
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self.half_period();
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self.scl_oe(true);
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}
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self.sda_oe(false);
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self.half_period();
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self.scl_oe(false);
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self.half_period();
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// Read ack/nack
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let ack = !self.sda_i();
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self.scl_oe(true);
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self.sda_oe(true);
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// postcondition: SCL and SDA low
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Ok(ack)
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}
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pub fn read(&mut self, ack: bool) -> Result<u8, &'static str> {
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// precondition: SCL and SDA low
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self.sda_oe(false);
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let mut data: u8 = 0;
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// MSB first
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for bit in (0..8).rev() {
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self.half_period();
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self.scl_oe(false);
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self.half_period();
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if self.sda_i() { data |= 1 << bit }
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self.scl_oe(true);
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}
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// Send ack/nack
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self.sda_oe(ack);
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self.half_period();
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self.scl_oe(false);
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self.half_period();
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self.scl_oe(true);
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self.sda_oe(true);
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// postcondition: SCL and SDA low
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Ok(data)
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}
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pub fn pca9548_select(&mut self, address: u8, channels: u8) -> Result<(), &'static str> {
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self.start()?;
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if !self.write(address << 1)? {
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return Err("PCA9548 failed to ack write address")
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}
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if !self.write(channels)? {
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return Err("PCA9548 failed to ack control word")
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}
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self.stop()?;
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Ok(())
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}
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}
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