2019-11-14 09:11:58 +08:00
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///! Register definitions for Application Processing Unit (mpcore)
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2019-11-16 06:54:26 +08:00
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use volatile_register::{RO, RW};
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2019-12-18 06:35:58 +08:00
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use libregister::{
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register, register_at, register_bit, register_bits,
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RegisterW, RegisterRW,
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};
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2019-11-14 09:11:58 +08:00
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#[repr(C)]
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pub struct RegisterBlock {
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2020-07-29 15:54:57 +08:00
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/// SCU Control Register
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2019-11-14 09:11:58 +08:00
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pub scu_control: ScuControl,
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2020-07-29 15:54:57 +08:00
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/// SCU Configuration Register
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pub scu_config: ScuConfig,
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/// SCU CPU Power Status Register
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pub scu_cpu_power_status: SCUCPUPowerStatusRegister,
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/// SCU Invalidate All Registers in Secure State
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2019-11-16 06:54:26 +08:00
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pub scu_invalidate: ScuInvalidate,
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2020-07-29 15:54:57 +08:00
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unused0: [u32; 12],
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/// Filtering Start Address Register
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pub filtering_start_address: FilteringStartAddressRegister,
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/// Defined by FILTEREND input
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pub filtering_end_address: FilteringEndAddressRegister,
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unused1: [u32; 2],
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/// SCU Access Control (SAC) Register
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pub scu_access_control_sac: SCUAccessControlRegisterSAC,
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/// SCU Non-secure Access Control Register SNSAC
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pub scu_non_secure_access_control: SCUNonSecureAccessControlRegister,
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unused2: [u32; 42],
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/// CPU Interface Control Register
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pub iccicr: ICCICR,
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/// Interrupt Priority Mask Register
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pub iccpmr: ICCPMR,
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/// Binary Point Register
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pub iccbpr: ICCBPR,
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/// Interrupt Acknowledge Register
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pub icciar: ICCIAR,
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/// End Of Interrupt Register
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pub icceoir: ICCEOIR,
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/// Running Priority Register
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pub iccrpr: ICCRPR,
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/// Highest Pending Interrupt Register
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pub icchpir: ICCHPIR,
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/// Aliased Non-secure Binary Point Register
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pub iccabpr: ICCABPR,
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unused3: [u32; 55],
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/// CPU Interface Implementer Identification Register
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pub iccidr: ICCIDR,
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/// Global Timer Counter Register 0
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2020-04-25 06:18:45 +08:00
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pub global_timer_counter0: ValueRegister,
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pub global_timer_counter1: ValueRegister,
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2020-07-29 15:54:57 +08:00
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/// Global Timer Control Register
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2020-04-25 06:18:45 +08:00
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pub global_timer_control: GlobalTimerControl,
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2020-07-29 15:54:57 +08:00
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/// Global Timer Interrupt Status Register
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pub global_timer_interrupt_status: GlobalTimerInterruptStatusRegister,
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/// Comparator Value Register_0
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2020-04-25 06:18:45 +08:00
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pub comparator_value0: ValueRegister,
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pub comparator_value1: ValueRegister,
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2020-07-29 15:54:57 +08:00
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/// Auto-increment Register
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pub auto_increment: RW<u32>,
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unused4: [u32; 249],
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/// Private Timer Load Register
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pub private_timer_load: RW<u32>,
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/// Private Timer Counter Register
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pub private_timer_counter: RW<u32>,
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/// Private Timer Control Register
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pub private_timer_control: PrivateTimerControlRegister,
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/// Private Timer Interrupt Status Register
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pub private_timer_interrupt_status: PrivateTimerInterruptStatusRegister,
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unused5: [u32; 4],
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/// Watchdog Load Register
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pub watchdog_load: RW<u32>,
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/// Watchdog Counter Register
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pub watchdog_counter: RW<u32>,
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/// Watchdog Control Register
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pub watchdog_control: WatchdogControlRegister,
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/// Watchdog Interrupt Status Register
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pub watchdog_interrupt_status: WatchdogInterruptStatusRegister,
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/// Watchdog Reset Status Register
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pub watchdog_reset_status: WatchdogResetStatusRegister,
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/// Watchdog Disable Register
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pub watchdog_disable: RW<u32>,
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unused6: [u32; 626],
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/// Distributor Control Register
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pub icddcr: ICDDCR,
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/// Interrupt Controller Type Register
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pub icdictr: ICDICTR,
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/// Distributor Implementer Identification Register
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pub icdiidr: ICDIIDR,
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unused7: [u32; 29],
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/// Interrupt Security Register
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pub icdisr0: RW<u32>,
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pub icdisr1: RW<u32>,
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pub icdisr2: RW<u32>,
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unused8: [u32; 29],
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2020-07-31 06:01:48 +08:00
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/// Interrupt Set-enable Registers
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pub icdiser: [RW<u32>; 3],
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2020-07-29 15:54:57 +08:00
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unused9: [u32; 29],
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/// Interrupt Clear-Enable Register 0
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pub icdicer0: RW<u32>,
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/// Interrupt Clear-Enable Register 1
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pub icdicer1: RW<u32>,
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/// Interrupt Clear-Enable Register 2
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pub icdicer2: RW<u32>,
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unused10: [u32; 29],
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/// Interrupt Set-pending Register
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pub icdispr0: RW<u32>,
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pub icdispr1: RW<u32>,
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pub icdispr2: RW<u32>,
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unused11: [u32; 29],
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/// Interrupt Clear-Pending Register
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pub icdicpr0: RW<u32>,
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pub icdicpr1: RW<u32>,
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pub icdicpr2: RW<u32>,
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unused12: [u32; 29],
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/// Active Bit register
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pub icdabr0: RW<u32>,
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pub icdabr1: RW<u32>,
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pub icdabr2: RW<u32>,
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unused13: [u32; 61],
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/// Interrupt Priority Register
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2020-08-03 11:19:54 +08:00
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pub icdipr: [RW<u32>; 24],
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2020-07-29 15:54:57 +08:00
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unused14: [u32; 232],
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2020-07-31 06:01:48 +08:00
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/// Interrupt Processor Targets Registers
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pub icdiptr: [RW<u32>; 24],
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2020-07-29 15:54:57 +08:00
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unused15: [u32; 232],
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2020-07-31 06:01:48 +08:00
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/// Interrupt Configuration Registers
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pub icdicfr: [RW<u32>; 6],
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2020-07-29 15:54:57 +08:00
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unused16: [u32; 58],
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/// PPI Status Register
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pub ppi_status: PpiStatus,
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/// SPI Status Register 0
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pub spi_status_0: RO<u32>,
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/// SPI Status Register 1
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pub spi_status_1: RO<u32>,
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unused17: [u32; 125],
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/// Software Generated Interrupt Register
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pub icdsgir: ICDSGIR,
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2019-11-14 09:11:58 +08:00
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}
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2020-07-29 15:54:57 +08:00
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2020-08-13 13:39:04 +08:00
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register_at!(RegisterBlock, 0xF8F00000, mpcore);
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2019-11-14 09:11:58 +08:00
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2020-07-29 15:54:57 +08:00
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register!(value_register, ValueRegister, RW, u32);
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register_bits!(value_register, value, u32, 0, 31);
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2019-11-14 09:11:58 +08:00
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register!(scu_control, ScuControl, RW, u32);
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register_bit!(scu_control, ic_standby_enable, 6);
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register_bit!(scu_control, scu_standby_enable, 5);
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register_bit!(scu_control, force_to_port0_enable, 4);
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register_bit!(scu_control, scu_speculative_linefill_enable, 3);
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register_bit!(scu_control, scu_rams_parity_enable, 2);
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register_bit!(scu_control, address_filtering_enable, 1);
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register_bit!(scu_control, enable, 0);
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2019-11-16 06:54:26 +08:00
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impl ScuControl {
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pub fn start(&mut self) {
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2020-09-07 16:12:56 +08:00
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self.modify(|_, w| w.enable(true).scu_speculative_linefill_enable(true));
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2019-11-16 06:54:26 +08:00
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}
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}
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2020-07-29 15:54:57 +08:00
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register!(scu_config, ScuConfig, RO, u32);
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register_bits!(scu_config, tag_ram_sizes, u8, 8, 15);
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register_bits!(scu_config, cpus_smp, u8, 4, 7);
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register_bits!(scu_config, cpu_number, u8, 0, 1);
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register!(scu_cpu_power_status, SCUCPUPowerStatusRegister, RW, u32);
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register_bits!(scu_cpu_power_status, cpu3_status, u8, 24, 25);
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register_bits!(scu_cpu_power_status, cpu2_status, u8, 16, 17);
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register_bits!(scu_cpu_power_status, cpu1_status, u8, 8, 9);
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register_bits!(scu_cpu_power_status, cpu0_status, u8, 0, 1);
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2019-11-16 06:54:26 +08:00
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register!(scu_invalidate, ScuInvalidate, WO, u32);
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register_bits!(scu_invalidate, cpu0_ways, u8, 0, 3);
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register_bits!(scu_invalidate, cpu1_ways, u8, 4, 7);
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register_bits!(scu_invalidate, cpu2_ways, u8, 8, 11);
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register_bits!(scu_invalidate, cpu3_ways, u8, 12, 15);
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impl ScuInvalidate {
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pub fn invalidate_all_cores(&mut self) {
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self.write(ScuInvalidate::zeroed()
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.cpu0_ways(0xf)
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.cpu1_ways(0xf)
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.cpu2_ways(0xf)
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.cpu3_ways(0xf)
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);
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}
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pub fn invalidate_core1(&mut self) {
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self.write(ScuInvalidate::zeroed()
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.cpu1_ways(0xf)
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);
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}
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}
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2020-04-25 06:18:45 +08:00
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2020-07-29 15:54:57 +08:00
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register!(filtering_start_address, FilteringStartAddressRegister, RW, u32);
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register_bits!(filtering_start_address, filtering_start_address, u32, 20, 31);
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register_bits!(filtering_start_address, sbz, u32, 0, 19);
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register!(filtering_end_address, FilteringEndAddressRegister, RW, u32);
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register_bits!(filtering_end_address, filtering_end_address, u32, 20, 31);
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register_bits!(filtering_end_address, sbz, u32, 0, 19);
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register!(scu_access_control_sac, SCUAccessControlRegisterSAC, RW, u32);
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register_bit!(scu_access_control_sac, cp_u3, 3);
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register_bit!(scu_access_control_sac, cp_u2, 2);
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register_bit!(scu_access_control_sac, cp_u1, 1);
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register_bit!(scu_access_control_sac, cp_u0, 0);
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register!(scu_non_secure_access_control, SCUNonSecureAccessControlRegister, RO, u32);
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register_bits!(scu_non_secure_access_control, sbz, u32, 12, 31);
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register_bit!(scu_non_secure_access_control, cpu3_global_timer, 11);
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register_bit!(scu_non_secure_access_control, cpu2_global_timer, 10);
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register_bit!(scu_non_secure_access_control, cpu1_global_timer, 9);
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register_bit!(scu_non_secure_access_control, cpu0_global_timer, 8);
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register_bit!(scu_non_secure_access_control, private_timers_for_cpu3, 7);
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register_bit!(scu_non_secure_access_control, private_timers_for_cpu2, 6);
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register_bit!(scu_non_secure_access_control, private_timers_for_cpu1, 5);
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register_bit!(scu_non_secure_access_control, private_timers_for_cpu0, 4);
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register_bit!(scu_non_secure_access_control, component_access_for_cpu3, 3);
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register_bit!(scu_non_secure_access_control, component_access_for_cpu2, 2);
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register_bit!(scu_non_secure_access_control, component_access_for_cpu1, 1);
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register_bit!(scu_non_secure_access_control, component_access_for_cpu0, 0);
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register!(iccicr, ICCICR, RW, u32);
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register_bit!(iccicr, sbpr, 4);
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register_bit!(iccicr, fiq_en, 3);
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register_bit!(iccicr, ack_ctl, 2);
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register_bit!(iccicr, enable_ns, 1);
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register_bit!(iccicr, enable_s, 0);
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register!(iccpmr, ICCPMR, RW, u32);
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register_bits!(iccpmr, priority, u8, 0, 7);
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register!(iccbpr, ICCBPR, RW, u32);
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register_bits!(iccbpr, binary_point, u8, 0, 2);
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register!(icciar, ICCIAR, RW, u32);
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register_bits!(icciar, cpuid, u8, 10, 12);
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register_bits!(icciar, ackintid, u32, 0, 9);
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register!(icceoir, ICCEOIR, RW, u32);
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register_bits!(icceoir, cpuid, u8, 10, 12);
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register_bits!(icceoir, eoiintid, u32, 0, 9);
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register!(iccrpr, ICCRPR, RW, u32);
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register_bits!(iccrpr, priority, u8, 0, 7);
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register!(icchpir, ICCHPIR, RW, u32);
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register_bits!(icchpir, cpuid, u8, 10, 12);
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register_bits!(icchpir, pendintid, u32, 0, 9);
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register!(iccabpr, ICCABPR, RW, u32);
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register_bits!(iccabpr, binary_point, u8, 0, 2);
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register!(iccidr, ICCIDR, RO, u32);
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register_bits!(iccidr, part_number, u32, 20, 31);
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register_bits!(iccidr, architecture_version, u8, 16, 19);
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register_bits!(iccidr, revision_number, u8, 12, 15);
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register_bits!(iccidr, implementer, u32, 0, 11);
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2020-04-25 06:18:45 +08:00
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register!(global_timer_control, GlobalTimerControl, RW, u32);
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2020-04-25 08:59:48 +08:00
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register_bits!(global_timer_control, prescaler, u8, 8, 15);
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2020-04-25 06:18:45 +08:00
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register_bit!(global_timer_control, auto_increment_mode, 3);
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register_bit!(global_timer_control, irq_enable, 2);
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register_bit!(global_timer_control, comp_enablea, 1);
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register_bit!(global_timer_control, timer_enable, 0);
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2020-07-29 15:54:57 +08:00
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register!(global_timer_interrupt_status, GlobalTimerInterruptStatusRegister, RW, u32);
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register_bit!(global_timer_interrupt_status, event_flag, 0);
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register!(private_timer_control, PrivateTimerControlRegister, RW, u32);
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|
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register_bits!(private_timer_control, sbzp, u32, 16, 31);
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|
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register_bits!(private_timer_control, prescaler, u8, 8, 15);
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|
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|
register_bits!(private_timer_control, unk_sbzp, u8, 3, 7);
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|
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|
register_bit!(private_timer_control, irq_enable, 2);
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|
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|
register_bit!(private_timer_control, auto_reload, 1);
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|
|
|
register_bit!(private_timer_control, timer_enable, 0);
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register!(private_timer_interrupt_status, PrivateTimerInterruptStatusRegister, RW, u32);
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|
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|
register_bits!(private_timer_interrupt_status, unk_sbzp, u32, 1, 31);
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|
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|
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|
register!(watchdog_control, WatchdogControlRegister, RW, u32);
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|
|
|
register_bits!(watchdog_control, prescaler, u8, 8, 15);
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|
|
|
|
register_bit!(watchdog_control, watchdog_mode, 3);
|
|
|
|
|
register_bit!(watchdog_control, it_enable, 2);
|
|
|
|
|
register_bit!(watchdog_control, auto_reload, 1);
|
|
|
|
|
register_bit!(watchdog_control, watchdog_enable, 0);
|
|
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|
|
|
|
|
|
|
register!(watchdog_interrupt_status, WatchdogInterruptStatusRegister, RW, u32);
|
|
|
|
|
register_bit!(watchdog_interrupt_status, event_flag, 0);
|
|
|
|
|
|
|
|
|
|
register!(watchdog_reset_status, WatchdogResetStatusRegister, RW, u32);
|
|
|
|
|
register_bit!(watchdog_reset_status, reset_flag, 0);
|
|
|
|
|
|
|
|
|
|
register!(icddcr, ICDDCR, RW, u32);
|
|
|
|
|
register_bit!(icddcr, enable_non_secure, 1);
|
|
|
|
|
register_bit!(icddcr, enable_secure, 0);
|
|
|
|
|
|
|
|
|
|
register!(icdictr, ICDICTR, RO, u32);
|
|
|
|
|
register_bits!(icdictr, lspi, u8, 11, 15);
|
|
|
|
|
register_bit!(icdictr, security_extn, 10);
|
|
|
|
|
register_bits!(icdictr, sbz, u8, 8, 9);
|
|
|
|
|
register_bits!(icdictr, cpu_number, u8, 5, 7);
|
|
|
|
|
register_bits!(icdictr, it_lines_number, u8, 0, 4);
|
|
|
|
|
|
|
|
|
|
register!(icdiidr, ICDIIDR, RO, u32);
|
|
|
|
|
register_bits!(icdiidr, implementation_version, u8, 24, 31);
|
|
|
|
|
register_bits!(icdiidr, revision_number, u32, 12, 23);
|
|
|
|
|
register_bits!(icdiidr, implementer, u32, 0, 11);
|
|
|
|
|
|
|
|
|
|
register!(ppi_status, PpiStatus, RO, u32);
|
|
|
|
|
register_bits!(ppi_status, ppi_status, u8, 11, 15);
|
|
|
|
|
register_bits!(ppi_status, sbz, u32, 0, 10);
|
|
|
|
|
|
|
|
|
|
register!(icdsgir, ICDSGIR, RW, u32);
|
|
|
|
|
register_bits!(icdsgir, target_list_filter, u8, 24, 25);
|
|
|
|
|
register_bits!(icdsgir, cpu_target_list, u8, 16, 23);
|
|
|
|
|
register_bit!(icdsgir, satt, 15);
|
|
|
|
|
register_bits!(icdsgir, sbz, u32, 4, 14);
|
|
|
|
|
register_bits!(icdsgir, sgiintid, u8, 0, 3);
|
|
|
|
|
|
