2019-05-05 20:56:23 +08:00
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use volatile_register::{RO, WO, RW};
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2019-05-21 05:01:50 +08:00
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use crate::{register, register_bit, register_bits, register_at, regs::*};
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2019-05-07 05:56:53 +08:00
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2019-05-21 07:30:54 +08:00
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pub enum ChannelMode {
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2019-05-22 07:42:24 +08:00
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Normal = 0b00,
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AutomaticEcho = 0b01,
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LocalLoopback = 0b10,
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2019-05-21 07:30:54 +08:00
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RemoteLoopback = 0b11,
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}
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2019-05-21 08:53:59 +08:00
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pub enum ParityMode {
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EvenParity = 0b000,
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OddParity = 0b001,
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ForceTo0 = 0b010,
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ForceTo1 = 0b011,
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2019-05-22 07:42:24 +08:00
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None = 0b100,
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2019-05-21 08:53:59 +08:00
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}
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2019-05-22 07:42:24 +08:00
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pub enum StopBits {
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One = 0b00,
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OneAndHalf = 0b01,
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Two = 0b10,
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}
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2019-05-21 08:53:59 +08:00
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2019-05-07 06:05:38 +08:00
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#[repr(C)]
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2019-05-05 20:56:23 +08:00
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pub struct RegisterBlock {
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2019-05-07 23:46:37 +08:00
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pub control: Control,
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pub mode: Mode,
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pub intrpt_en: RW<u32>,
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pub intrpt_dis: RW<u32>,
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pub intrpt_mask: RO<u32>,
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pub chnl_int_sts: WO<u32>,
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pub baud_rate_gen: BaudRateGen,
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pub rcvr_timeout: RW<u32>,
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pub rcvr_fifo_trigger_level: RW<u32>,
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pub modem_ctrl: RW<u32>,
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pub modem_sts: RW<u32>,
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pub channel_sts: ChannelSts,
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pub tx_rx_fifo: TxRxFifo,
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pub baud_rate_divider: BaudRateDiv,
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pub flow_delay: RW<u32>,
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pub unused0: RO<u32>,
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pub unused1: RO<u32>,
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pub tx_fifo_trigger_level: RW<u32>,
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2019-05-05 20:56:23 +08:00
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}
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2019-05-21 05:01:50 +08:00
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register_at!(RegisterBlock, 0xE0000000, uart0);
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register_at!(RegisterBlock, 0xE0001000, uart1);
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2019-05-05 20:56:23 +08:00
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2019-05-07 06:32:45 +08:00
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register!(control, Control, RW, u32);
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2019-05-07 05:56:53 +08:00
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register_bit!(control, rxrst, 0);
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register_bit!(control, txrst, 1);
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register_bit!(control, rxen, 2);
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register_bit!(control, rxdis, 3);
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register_bit!(control, txen, 4);
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register_bit!(control, txdis, 5);
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2019-05-21 07:30:54 +08:00
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register_bit!(control, rstto, 6);
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register_bit!(control, sttbrk, 7);
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register_bit!(control, stpbrk, 8);
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2019-05-07 05:56:53 +08:00
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2019-05-07 06:32:45 +08:00
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register!(mode, Mode, RW, u32);
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2019-05-21 07:30:54 +08:00
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/// Channel mode: Defines the mode of operation of the UART.
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register_bits!(mode, chmode, u8, 8, 9);
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2019-05-22 07:42:24 +08:00
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/// Number of stop bits
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register_bits!(mode, nbstop, u8, 6, 7);
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/// Parity type select
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2019-05-07 05:56:53 +08:00
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register_bits!(mode, par, u8, 3, 5);
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2019-05-22 07:42:24 +08:00
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/// Character length select
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register_bits!(mode, chrl, u8, 1, 2);
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/// Clock source select
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register_bit!(mode, clks, 0);
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2019-05-07 05:56:53 +08:00
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2019-05-07 06:32:45 +08:00
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register!(baud_rate_gen, BaudRateGen, RW, u32);
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2019-05-07 05:56:53 +08:00
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register_bits!(baud_rate_gen, cd, u16, 0, 15);
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2019-05-07 06:32:45 +08:00
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register!(channel_sts, ChannelSts, RO, u32);
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2019-05-07 05:56:53 +08:00
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register_bit!(channel_sts, txfull, 4);
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2019-05-07 06:32:45 +08:00
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register!(tx_rx_fifo, TxRxFifo, RW, u32);
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2019-05-07 05:56:53 +08:00
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register_bits!(tx_rx_fifo, data, u32, 0, 31);
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2019-05-07 06:32:45 +08:00
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register!(baud_rate_div, BaudRateDiv, RW, u32);
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2019-05-07 05:56:53 +08:00
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register_bits!(baud_rate_div, bdiv, u8, 0, 7);
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