forked from M-Labs/zynq-rs
1
0
Fork 0
zynq-rs/experiments/src/main.rs

263 lines
8.1 KiB
Rust
Raw Normal View History

2019-05-05 20:56:23 +08:00
#![no_std]
#![no_main]
2020-03-31 07:16:58 +08:00
extern crate alloc;
use core::{mem::transmute, task::Poll};
use alloc::{borrow::ToOwned, collections::BTreeMap, format};
use log::info;
use libregister::RegisterR;
2020-04-09 08:49:24 +08:00
use libcortex_a9::{mutex::Mutex, sync_channel::{self, sync_channel}};
use libboard_zynq::{
print, println,
self as zynq, clocks::Clocks, clocks::source::{ClockSource, ArmPll, IoPll},
smoltcp::{
self,
wire::{EthernetAddress, IpAddress, IpCidr},
2020-03-31 07:16:58 +08:00
iface::{NeighborCache, EthernetInterfaceBuilder, Routes},
time::Instant,
},
time::Milliseconds,
};
use libsupport_zynq::{
ram, alloc::{vec, vec::Vec},
boot,
};
use libasync::{delay, smoltcp::{Sockets, TcpStream}, task};
2019-05-05 20:56:23 +08:00
mod ps7_init;
const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
#[no_mangle]
pub fn main_core0() {
2019-12-17 08:07:46 +08:00
// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
println!("\nzc706 main");
libboard_zynq::logger::init().unwrap();
log::set_max_level(log::LevelFilter::Trace);
info!("Boot mode: {:?}", zynq::slcr::RegisterBlock::new().boot_mode.read().boot_mode_pins());
#[cfg(feature = "target_zc706")]
const CPU_FREQ: u32 = 800_000_000;
#[cfg(feature = "target_cora_z7_10")]
const CPU_FREQ: u32 = 650_000_000;
println!("Setup clock sources...");
ArmPll::setup(2 * CPU_FREQ);
Clocks::set_cpu_freq(CPU_FREQ);
#[cfg(feature = "target_zc706")]
{
IoPll::setup(1_000_000_000);
libboard_zynq::stdio::drop_uart();
}
println!("PLLs set up");
let clocks = zynq::clocks::Clocks::get();
println!("CPU Clocks: {}/{}/{}/{}", clocks.cpu_6x4x(), clocks.cpu_3x2x(), clocks.cpu_2x(), clocks.cpu_1x());
let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode();
let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) };
for i in 0..=1 {
print!("Flash {}:", i);
for b in &flash_ram[(i * 16 * 1024 * 1024)..][..128] {
print!(" {:02X}", *b);
}
println!("");
}
let mut flash = flash.stop();
let timer = libboard_zynq::timer::GlobalTimer::start();
2019-10-26 05:19:34 +08:00
let mut ddr = zynq::ddr::DdrRam::new();
2019-12-17 08:07:46 +08:00
#[cfg(not(feature = "target_zc706"))]
2019-10-26 05:19:34 +08:00
ddr.memtest();
ram::init_alloc_ddr(&mut ddr);
#[cfg(dev)]
for i in 0..=1 {
let mut flash_io = flash.manual_mode(i);
2019-12-17 08:07:46 +08:00
// println!("rdcr={:02X}", flash_io.rdcr());
print!("Flash {} ID:", i);
for b in flash_io.rdid() {
print!(" {:02X}", b);
}
println!("");
print!("Flash {} I/O:", i);
2019-12-17 08:07:46 +08:00
for o in 0..8 {
const CHUNK: u32 = 8;
for b in flash_io.read(CHUNK * o, CHUNK as usize) {
print!(" {:02X}", b);
}
}
println!("");
2019-12-17 08:07:46 +08:00
flash_io.dump("Read cr1", 0x35);
flash_io.dump("Read Autoboot", 0x14);
flash_io.dump("Read Bank", 0x16);
flash_io.dump("DLP Bank", 0x16);
flash_io.dump("Read ESig", 0xAB);
flash_io.dump("OTP Read", 0x4B);
flash_io.dump("DYB Read", 0xE0);
flash_io.dump("PPB Read", 0xE2);
flash_io.dump("ASP Read", 0x2B);
flash_io.dump("Password Read", 0xE7);
flash_io.write_enabled(|flash_io| {
flash_io.erase(0);
});
flash_io.write_enabled(|flash_io| {
2020-05-01 07:17:53 +08:00
flash_io.program(0, [0x23054223; 0x100 >> 2].iter().cloned());
2019-12-17 08:07:46 +08:00
});
flash = flash_io.stop();
}
2019-12-17 08:07:46 +08:00
2020-04-28 19:31:49 +08:00
let core1 = boot::Core1::start();
2019-12-17 08:07:46 +08:00
let (mut core1_req, rx) = sync_channel(10);
*CORE1_REQ.lock() = Some(rx);
let (tx, mut core1_res) = sync_channel(10);
*CORE1_RES.lock() = Some(tx);
task::block_on(async {
for i in 0..10 {
core1_req.async_send(i).await;
let j = core1_res.async_recv().await;
println!("{} -> {}", i, j);
2020-04-09 08:49:24 +08:00
}
});
core1.disable();
2019-12-17 08:07:46 +08:00
let eth = zynq::eth::Eth::default(HWADDR.clone());
2019-06-20 06:30:18 +08:00
println!("Eth on");
2019-05-08 01:28:33 +08:00
2019-11-01 02:20:49 +08:00
const RX_LEN: usize = 8;
let mut rx_descs = (0..RX_LEN)
.map(|_| zynq::eth::rx::DescEntry::zeroed())
.collect::<Vec<_>>();
2020-03-31 07:16:58 +08:00
let mut rx_buffers = vec![zynq::eth::Buffer::new(); RX_LEN];
2019-09-29 07:39:57 +08:00
// Number of transmission buffers (minimum is two because with
// one, duplicate packet transmission occurs)
2019-11-01 02:20:49 +08:00
const TX_LEN: usize = 8;
let mut tx_descs = (0..TX_LEN)
.map(|_| zynq::eth::tx::DescEntry::zeroed())
.collect::<Vec<_>>();
2020-03-31 07:16:58 +08:00
let mut tx_buffers = vec![zynq::eth::Buffer::new(); TX_LEN];
2019-08-11 06:55:27 +08:00
let eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
2020-03-31 07:16:58 +08:00
// let mut eth = eth.start_tx(&mut tx_descs, &mut tx_buffers);
let mut eth = eth.start_tx(
// HACK
2019-11-01 02:20:49 +08:00
unsafe { transmute(tx_descs.as_mut_slice()) },
unsafe { transmute(tx_buffers.as_mut_slice()) },
);
2020-05-01 07:17:53 +08:00
let ethernet_addr = EthernetAddress(HWADDR);
// IP stack
let local_addr = IpAddress::v4(192, 168, 1, 51);
let mut ip_addrs = [IpCidr::new(local_addr, 24)];
2020-05-01 07:17:53 +08:00
let routes = Routes::new(BTreeMap::new());
let neighbor_cache = NeighborCache::new(BTreeMap::new());
let mut iface = EthernetInterfaceBuilder::new(&mut eth)
.ethernet_addr(ethernet_addr)
.ip_addrs(&mut ip_addrs[..])
2020-03-31 07:16:58 +08:00
.routes(routes)
.neighbor_cache(neighbor_cache)
.finalize();
2020-03-31 07:16:58 +08:00
2020-05-01 07:17:53 +08:00
ps7_init::report_differences();
2020-03-31 07:16:58 +08:00
Sockets::init(32);
2019-12-17 08:07:46 +08:00
/// `chargen`
const TCP_PORT: u16 = 19;
async fn handle_connection(stream: TcpStream) -> smoltcp::Result<()> {
stream.send("Enter your name: ".bytes()).await?;
let name = stream.recv(|buf| {
for (i, b) in buf.iter().enumerate() {
if *b == '\n' as u8 {
return match core::str::from_utf8(&buf[0..i]) {
Ok(name) =>
Poll::Ready((i + 1, Some(name.to_owned()))),
Err(_) =>
Poll::Ready((i + 1, None))
};
}
}
if buf.len() > 100 {
// Too much input, consume all
Poll::Ready((buf.len(), None))
} else {
Poll::Pending
}
}).await?;
match name {
Some(name) =>
stream.send(format!("Hello {}!\n", name).bytes()).await?,
None =>
stream.send("I had trouble reading your name.\n".bytes()).await?,
}
2020-05-01 07:17:53 +08:00
let _ = stream.flush().await;
Ok(())
}
2020-05-01 07:17:53 +08:00
let counter = alloc::rc::Rc::new(core::cell::RefCell::new(0));
task::spawn(async move {
2020-05-01 07:17:53 +08:00
while let Ok(stream) = TcpStream::accept(TCP_PORT, 2048, 2408).await {
let counter = counter.clone();
task::spawn(async move {
*counter.borrow_mut() += 1;
println!("Serving {} connections", *counter.borrow());
handle_connection(stream)
.await
2020-05-01 07:17:53 +08:00
.unwrap_or_else(|e| println!("Connection: {:?}", e));
*counter.borrow_mut() -= 1;
println!("Now serving {} connections", *counter.borrow());
});
}
2020-03-31 07:16:58 +08:00
});
2019-12-17 08:07:46 +08:00
let mut countdown = timer.countdown();
task::spawn(async move {
loop {
delay(&mut countdown, Milliseconds(1000)).await;
let timestamp = timer.get_us();
let seconds = timestamp / 1_000_000;
let micros = timestamp % 1_000_000;
println!("time: {:6}.{:06}s", seconds, micros);
}
});
2020-04-03 06:18:04 +08:00
Sockets::run(&mut iface, || {
Instant::from_millis(timer.get_time().0 as i64)
2020-04-17 02:42:21 +08:00
})
2019-05-28 06:28:35 +08:00
}
2019-05-31 02:30:19 +08:00
static CORE1_REQ: Mutex<Option<sync_channel::Receiver<usize>>> = Mutex::new(None);
static CORE1_RES: Mutex<Option<sync_channel::Sender<usize>>> = Mutex::new(None);
2019-12-17 08:07:46 +08:00
static DONE: Mutex<bool> = Mutex::new(false);
#[no_mangle]
2019-11-16 07:21:57 +08:00
pub fn main_core1() {
2019-11-21 00:00:57 +08:00
println!("Hello from core1!");
2020-04-09 08:49:24 +08:00
let mut req = None;
while req.is_none() {
req = CORE1_REQ.lock().take();
}
2020-05-01 07:17:53 +08:00
let req = req.unwrap();
let mut res = None;
while res.is_none() {
res = CORE1_RES.lock().take();
2020-04-09 08:49:24 +08:00
}
let mut res = res.unwrap();
2020-04-09 08:49:24 +08:00
for i in req {
res.send(*i * *i);
2019-12-17 08:07:46 +08:00
}
2020-04-09 08:49:24 +08:00
2019-12-17 08:07:46 +08:00
println!("core1 done!");
*DONE.lock() = true;
2019-11-16 07:21:57 +08:00
loop {}
}