diff --git a/src/runtime/src/rtio_clocking.rs b/src/runtime/src/rtio_clocking.rs
index db3b3fa..f91c182 100644
--- a/src/runtime/src/rtio_clocking.rs
+++ b/src/runtime/src/rtio_clocking.rs
@@ -454,10 +454,7 @@ fn set_fclk0_freq(clk: RtioClock, cfg: &Config) {
                 .modify(|_, w| w.divisor0(divisor0).divisor1(divisor1));
         });
     } else {
-        warn!(
-            "Could not set fclk0 for target frequency of '{:?}' with available divisors",
-            target_freq
-        );
+        warn!("Could not set fclk0 for target frequency of '{:?}'", target_freq);
     }
 }
 
@@ -489,7 +486,6 @@ pub fn init(timer: &mut GlobalTimer, cfg: &Config) {
 
     #[cfg(feature = "target_ebaz4205")]
     {
-        // Set FPGA0_FCLK
         match clk {
             RtioClock::Int_100 | RtioClock::Int_125 | RtioClock::Int_150 => {
                 set_fclk0_freq(clk, cfg);