forked from M-Labs/artiq-zynq
Remove commented code for PHY xtal.
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@ -87,16 +87,7 @@ class EBAZ4205(SoCCore):
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platform.add_extension(_ps)
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platform.add_extension(_ps)
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platform.add_extension(_ddr)
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platform.add_extension(_ddr)
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## Uncomment if your EBAZ4205 doesn't have a PHY XTAL
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## Clock for PHY is tied to pin U18
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# platform.add_extension(
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# [
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# ("phy_clk", 0, Pins("U18"), IOStandard("LVCMOS33")),
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# ]
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# )
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gmii = platform.request("gmii")
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gmii = platform.request("gmii")
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platform.add_period_constraint(gmii.rx_clk, 10)
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platform.add_period_constraint(gmii.rx_clk, 10)
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platform.add_period_constraint(gmii.tx_clk, 10)
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platform.add_period_constraint(gmii.tx_clk, 10)
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platform.add_platform_command(
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platform.add_platform_command(
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@ -135,11 +126,6 @@ class EBAZ4205(SoCCore):
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self.ps7.enet0.enet.gmii.rx_dv.eq(gmii.rx_dv),
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self.ps7.enet0.enet.gmii.rx_dv.eq(gmii.rx_dv),
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]
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]
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## Uncomment if your EBAZ4205 doesn't have a PHY XTAL
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## Left for the user to do, setup a 25 MHz clock for phy_clk.
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# phy_clk = platform.request("phy_clk")
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# ...
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# MDIO
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# MDIO
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mdio = platform.request("mdio")
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mdio = platform.request("mdio")
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self.comb += [
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self.comb += [
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